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Mon, 12 Mar 2018 21:01:02 +0000 From: Babu Moger To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, rkrcmar@redhat.com Cc: mtosatti@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org, Gary.Hook@amd.com, Thomas.Lendacky@amd.com, brijesh.singh@amd.com, babu.moger@amd.com, kash@tripleback.net Subject: [PATCH v4 1/5] target/i386: Generalize some of the macro definitions Date: Mon, 12 Mar 2018 17:00:45 -0400 Message-Id: <1520888449-4352-2-git-send-email-babu.moger@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1520888449-4352-1-git-send-email-babu.moger@amd.com> References: <1520888449-4352-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BN6PR1201CA0019.namprd12.prod.outlook.com (2603:10b6:405:4c::29) To MWHPR12MB1774.namprd12.prod.outlook.com (2603:10b6:300:112::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: bc3b195f-6d36-465d-33f3-08d5885c5dfa X-Microsoft-Antispam: UriScan:; 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Signed-off-by: Babu Moger --- target/i386/cpu.c | 52 ++++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5e431e..42dd381 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -66,22 +66,22 @@ #define CPUID_2_L3_16MB_16WAY_64B 0x4d -/* CPUID Leaf 4 constants: */ +/* Cache specific constants: */ /* EAX: */ -#define CPUID_4_TYPE_DCACHE 1 -#define CPUID_4_TYPE_ICACHE 2 -#define CPUID_4_TYPE_UNIFIED 3 +#define TYPE_DCACHE 1 +#define TYPE_ICACHE 2 +#define TYPE_UNIFIED 3 -#define CPUID_4_LEVEL(l) ((l) << 5) +#define CACHE_LEVEL(l) ((l) << 5) -#define CPUID_4_SELF_INIT_LEVEL (1 << 8) -#define CPUID_4_FULLY_ASSOC (1 << 9) +#define CACHE_SELF_INIT_LEVEL (1 << 8) +#define CACHE_FULLY_ASSOC (1 << 9) /* EDX: */ -#define CPUID_4_NO_INVD_SHARING (1 << 0) -#define CPUID_4_INCLUSIVE (1 << 1) -#define CPUID_4_COMPLEX_IDX (1 << 2) +#define CACHE_NO_INVD_SHARING (1 << 0) +#define CACHE_INCLUSIVE (1 << 1) +#define CACHE_COMPLEX_IDX (1 << 2) #define ASSOC_FULL 0xFF @@ -3273,29 +3273,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *eax = 0; switch (count) { case 0: /* L1 dcache info */ - *eax |= CPUID_4_TYPE_DCACHE | \ - CPUID_4_LEVEL(1) | \ - CPUID_4_SELF_INIT_LEVEL; + *eax |= TYPE_DCACHE | \ + CACHE_LEVEL(1) | \ + CACHE_SELF_INIT_LEVEL; *ebx = (L1D_LINE_SIZE - 1) | \ ((L1D_PARTITIONS - 1) << 12) | \ ((L1D_ASSOCIATIVITY - 1) << 22); *ecx = L1D_SETS - 1; - *edx = CPUID_4_NO_INVD_SHARING; + *edx = CACHE_NO_INVD_SHARING; break; case 1: /* L1 icache info */ - *eax |= CPUID_4_TYPE_ICACHE | \ - CPUID_4_LEVEL(1) | \ - CPUID_4_SELF_INIT_LEVEL; + *eax |= TYPE_ICACHE | \ + CACHE_LEVEL(1) | \ + CACHE_SELF_INIT_LEVEL; *ebx = (L1I_LINE_SIZE - 1) | \ ((L1I_PARTITIONS - 1) << 12) | \ ((L1I_ASSOCIATIVITY - 1) << 22); *ecx = L1I_SETS - 1; - *edx = CPUID_4_NO_INVD_SHARING; + *edx = CACHE_NO_INVD_SHARING; break; case 2: /* L2 cache info */ - *eax |= CPUID_4_TYPE_UNIFIED | \ - CPUID_4_LEVEL(2) | \ - CPUID_4_SELF_INIT_LEVEL; + *eax |= TYPE_UNIFIED | \ + CACHE_LEVEL(2) | \ + CACHE_SELF_INIT_LEVEL; if (cs->nr_threads > 1) { *eax |= (cs->nr_threads - 1) << 14; } @@ -3303,7 +3303,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, ((L2_PARTITIONS - 1) << 12) | \ ((L2_ASSOCIATIVITY - 1) << 22); *ecx = L2_SETS - 1; - *edx = CPUID_4_NO_INVD_SHARING; + *edx = CACHE_NO_INVD_SHARING; break; case 3: /* L3 cache info */ if (!cpu->enable_l3_cache) { @@ -3313,16 +3313,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = 0; break; } - *eax |= CPUID_4_TYPE_UNIFIED | \ - CPUID_4_LEVEL(3) | \ - CPUID_4_SELF_INIT_LEVEL; + *eax |= TYPE_UNIFIED | \ + CACHE_LEVEL(3) | \ + CACHE_SELF_INIT_LEVEL; pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); *eax |= ((1 << pkg_offset) - 1) << 14; *ebx = (L3_N_LINE_SIZE - 1) | \ ((L3_N_PARTITIONS - 1) << 12) | \ ((L3_N_ASSOCIATIVITY - 1) << 22); *ecx = L3_N_SETS - 1; - *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX; + *edx = CACHE_INCLUSIVE | CACHE_COMPLEX_IDX; break; default: /* end of info */ *eax = 0;