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Tue, 10 Apr 2018 23:16:24 +0000 From: Babu Moger To: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, kash@tripleback.net, geoff@hostfission.com, babu.moger@amd.com Subject: [PATCH v6 5/9] i386: Use the statically loaded cache definitions Date: Tue, 10 Apr 2018 19:16:05 -0400 Message-Id: <1523402169-113351-6-git-send-email-babu.moger@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1523402169-113351-1-git-send-email-babu.moger@amd.com> References: <1523402169-113351-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: MWHPR2201CA0048.namprd22.prod.outlook.com (2603:10b6:301:16::22) To CY4PR12MB1767.namprd12.prod.outlook.com (2603:10b6:903:122::9) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(5600026)(4534165)(4627221)(201703031133081)(201702281549075)(48565401081)(2017052603328)(7153060)(7193020); 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Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- target/i386/cpu.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1659320..76b3bc9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3934,8 +3934,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); - *ecx = encode_cache_cpuid80000005(&l1d_cache_amd); - *edx = encode_cache_cpuid80000005(&l1i_cache_amd); + if (env->cache_info.valid && !cpu->legacy_cache) { + *ecx = encode_cache_cpuid80000005(&env->cache_info.l1d_cache); + *edx = encode_cache_cpuid80000005(&env->cache_info.l1i_cache); + } else { + *ecx = encode_cache_cpuid80000005(&l1d_cache_amd); + *edx = encode_cache_cpuid80000005(&l1i_cache_amd); + } break; case 0x80000006: /* cache info (L2 cache) */ @@ -3951,9 +3956,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); - encode_cache_cpuid80000006(&l2_cache_amd, - cpu->enable_l3_cache ? &l3_cache : NULL, - ecx, edx); + if (env->cache_info.valid && !cpu->legacy_cache) { + encode_cache_cpuid80000006(&env->cache_info.l2_cache, + cpu->enable_l3_cache ? + &env->cache_info.l3_cache : NULL, + ecx, edx); + } else { + encode_cache_cpuid80000006(&l2_cache_amd, + cpu->enable_l3_cache ? &l3_cache : NULL, + ecx, edx); + } break; case 0x80000007: *eax = 0;