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Thu, 26 Apr 2018 16:27:02 +0000 From: Babu Moger To: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, kash@tripleback.net, geoff@hostfission.com, babu.moger@amd.com Subject: [PATCH v7 4/9] i386: Add new property to control cache info Date: Thu, 26 Apr 2018 11:26:44 -0500 Message-Id: <1524760009-24710-5-git-send-email-babu.moger@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524760009-24710-1-git-send-email-babu.moger@amd.com> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: CY4PR1801CA0020.namprd18.prod.outlook.com (2603:10b6:910:74::33) To SN1PR12MB2479.namprd12.prod.outlook.com (2603:10b6:802:29::18) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(5600026)(4534165)(4627221)(201703031133081)(201702281549075)(48565401081)(2017052603328)(7153060)(7193020); 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By default new information will be displayed. If user passes "-cpu legacy-cache" then older information will be displayed even if the hardware supports new information. It will be "on" for machine type "pc-q35-2.10" for compatibility. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- include/hw/i386/pc.h | 4 ++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 5 +++++ 3 files changed, 10 insertions(+) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ffee841..d904a3c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -327,6 +327,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "q35-pcihost",\ .property = "x-pci-hole64-fix",\ .value = "off",\ + },{\ + .driver = TYPE_X86_CPU,\ + .property = "legacy-cache",\ + .value = "on",\ }, #define PC_COMPAT_2_9 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5d88363..a27b658 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5138,6 +5138,7 @@ static Property x86_cpu_properties[] = { false), DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), + DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false), /* * From "Requirements for Implementing the Microsoft diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1213bb7..852586a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1395,6 +1395,11 @@ struct X86CPU { */ bool enable_l3_cache; + /* Compatibility bits for old machine types. + * If true present the old cache topology information + */ + bool legacy_cache; + /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb;