From patchwork Tue Jun 19 11:46:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 10474153 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BF3D460230 for ; Tue, 19 Jun 2018 11:47:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B966E28A59 for ; Tue, 19 Jun 2018 11:47:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AADA128B2D; Tue, 19 Jun 2018 11:47:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 05FB328A59 for ; Tue, 19 Jun 2018 11:47:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964997AbeFSLrx (ORCPT ); Tue, 19 Jun 2018 07:47:53 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:40044 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757189AbeFSLru (ORCPT ); Tue, 19 Jun 2018 07:47:50 -0400 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w5JBhfRf111250 for ; Tue, 19 Jun 2018 07:47:50 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jpydm4xq9-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 19 Jun 2018 07:47:50 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 19 Jun 2018 12:47:45 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w5JBliNH30081080 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Jun 2018 11:47:44 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8014AAE055; Tue, 19 Jun 2018 12:36:27 +0100 (BST) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52C1BAE04D; Tue, 19 Jun 2018 12:36:27 +0100 (BST) Received: from s38lp20.boeblingen.de.ibm.com (unknown [9.152.224.155]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 19 Jun 2018 12:36:27 +0100 (BST) From: Janosch Frank To: kvm@vger.kernel.org Cc: thuth@redhat.com, david@redhat.com Subject: [kvm-unit-tests PATCH] s390x: Catch all exceptions Date: Tue, 19 Jun 2018 13:46:53 +0200 X-Mailer: git-send-email 2.7.4 X-TM-AS-GCONF: 00 x-cbid: 18061911-0012-0000-0000-0000028110AB X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18061911-0013-0000-0000-000020B24A1A Message-Id: <1529408813-8724-1-git-send-email-frankja@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-19_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=517 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1805220000 definitions=main-1806190133 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Right now we only catch the exceptions that we really expect to receive. Let's at least catch all of them and abort if any of the unexpected ones fell on our foot. Signed-off-by: Janosch Frank --- lib/s390x/interrupt.c | 24 +++++++++++++++ s390x/cstart64.S | 82 +++++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 101 insertions(+), 5 deletions(-) diff --git a/lib/s390x/interrupt.c b/lib/s390x/interrupt.c index bc44e3a..848d5f2 100644 --- a/lib/s390x/interrupt.c +++ b/lib/s390x/interrupt.c @@ -104,3 +104,27 @@ void handle_pgm_int(void) pgm_int_expected = false; fixup_pgm_int(); } + +void handle_ext_int(void) +{ + report_abort("Unexpected external call interrupt: at %#lx", + lc->ext_old_psw.addr); +} + +void handle_mcck_int(void) +{ + report_abort("Unexpected machine check interrupt: at %#lx", + lc->mcck_old_psw.addr); +} + +void handle_io_int(void) +{ + report_abort("Unexpected io interrupt: at %#lx", + lc->io_old_psw.addr); +} + +void handle_svc_int(void) +{ + report_abort("Unexpected service call interrupt: at %#lx", + lc->svc_old_psw.addr); +} diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 9a26ed3..9cd5c1d 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -26,6 +26,18 @@ init_psw_cont: /* setup pgm interrupt handler */ larl %r1, pgm_int_psw mvc GEN_LC_PGM_NEW_PSW(16), 0(%r1) + /* setup ext interrupt handler */ + larl %r1, ext_int_psw + mvc GEN_LC_EXT_NEW_PSW(16), 0(%r1) + /* setup mcck interrupt handler */ + larl %r1, mcck_int_psw + mvc GEN_LC_MCCK_NEW_PSW(16), 0(%r1) + /* setup io interrupt handler */ + larl %r1, ext_int_psw + mvc GEN_LC_IO_NEW_PSW(16), 0(%r1) + /* setup svc interrupt handler */ + larl %r1, mcck_int_psw + mvc GEN_LC_SVC_NEW_PSW(16), 0(%r1) /* setup cr0, enabling e.g. AFP-register control */ larl %r1, initital_cr0 lctlg %c0, %c0, 0(%r1) @@ -42,9 +54,7 @@ init_psw_cont: /* call exit() */ j exit -pgm_int: - /* save grs 0-15 */ - stmg %r0, %r15, GEN_LC_SW_INT_GRS +save_fps: /* save fprs 0-15 + fpc */ larl %r1, GEN_LC_SW_INT_FPRS std %f0, 0(%r1) @@ -64,8 +74,9 @@ pgm_int: std %f14, 112(%r1) std %f15, 120(%r1) stfpc GEN_LC_SW_INT_FPC - /* call our c handler */ - brasl %r14, handle_pgm_int + bcr 15, %r14 + +restore_fps: /* restore fprs 0-15 + fpc */ larl %r1, GEN_LC_SW_INT_FPRS ld %f0, 0(%r1) @@ -85,15 +96,76 @@ pgm_int: ld %f14, 112(%r1) ld %f15, 120(%r1) lfpc GEN_LC_SW_INT_FPC + bcr 15, %r14 + +pgm_int: + /* save grs 0-15 */ + stmg %r0, %r15, GEN_LC_SW_INT_GRS + brasl %r14, save_fps + /* call our c handler */ + brasl %r14, handle_pgm_int + brasl %r14, restore_fps /* restore grs 0-15 */ lmg %r0, %r15, GEN_LC_SW_INT_GRS lpswe GEN_LC_PGM_OLD_PSW +ext_int: + /* save grs 0-15 */ + stmg %r0, %r15, GEN_LC_SW_INT_GRS + brasl %r14, save_fps + /* call our c handler */ + brasl %r14, handle_ext_int + brasl %r14, restore_fps + /* restore grs 0-15 */ + lmg %r0, %r15, GEN_LC_SW_INT_GRS + lpswe GEN_LC_EXT_OLD_PSW + +mcck_int: + /* save grs 0-15 */ + stmg %r0, %r15, GEN_LC_SW_INT_GRS + brasl %r14, save_fps + /* call our c handler */ + brasl %r14, handle_mcck_int + brasl %r14, restore_fps + /* restore grs 0-15 */ + lmg %r0, %r15, GEN_LC_SW_INT_GRS + lpswe GEN_LC_MCCK_OLD_PSW + +io_int: + /* save grs 0-15 */ + stmg %r0, %r15, GEN_LC_SW_INT_GRS + brasl %r14, save_fps + /* call our c handler */ + brasl %r14, handle_io_int + brasl %r14, restore_fps + /* restore grs 0-15 */ + lmg %r0, %r15, GEN_LC_SW_INT_GRS + lpswe GEN_LC_IO_OLD_PSW + +svc_int: + /* save grs 0-15 */ + stmg %r0, %r15, GEN_LC_SW_INT_GRS + brasl %r14, save_fps + /* call our c handler */ + brasl %r14, handle_svc_int + brasl %r14, restore_fps + /* restore grs 0-15 */ + lmg %r0, %r15, GEN_LC_SW_INT_GRS + lpswe GEN_LC_SVC_OLD_PSW + .align 8 initital_psw: .quad 0x0000000180000000, init_psw_cont pgm_int_psw: .quad 0x0000000180000000, pgm_int +ext_int_psw: + .quad 0x0000000180000000, ext_int +mcck_int_psw: + .quad 0x0000000180000000, mcck_int +io_int_psw: + .quad 0x0000000180000000, io_int +svc_int_psw: + .quad 0x0000000180000000, svc_int initital_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ .quad 0x0000000000040000