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[128.59.18.193]) by smtp.gmail.com with ESMTPSA id e131sm4888474qkb.80.2019.05.01.18.55.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 01 May 2019 18:55:27 -0700 (PDT) From: Jintack Lim To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, Jintack Lim Subject: [PATCH] KVM: nVMX: Set msr bitmap correctly for MSR_FS_BASE in vmcs02 Date: Wed, 1 May 2019 22:09:19 -0400 Message-Id: <1556762959-31705-1-git-send-email-jintack@cs.columbia.edu> X-Mailer: git-send-email 1.9.1 X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.84 on 128.59.72.14 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Even when neither L0 nor L1 configured to trap MSR_FS_BASE writes from its own VMs, the current KVM L0 always traps MSR_FS_BASE writes from L2. Let's check if both L0 and L1 disabled trap for MSR_FS_BASE for its VMs respectively, and let L2 write to MSR_FS_BASE without trap if that's the case. Signed-off-by: Jintack Lim --- arch/x86/kvm/vmx/nested.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 0c601d0..ab85aea 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -537,6 +537,7 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, */ bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD); bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL); + bool fs_base = !msr_write_intercepted_l01(vcpu, MSR_FS_BASE); /* Nothing to do if the MSR bitmap is not in use. */ if (!cpu_has_vmx_msr_bitmap() || @@ -592,6 +593,12 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, } } + if (fs_base) + nested_vmx_disable_intercept_for_msr( + msr_bitmap_l1, msr_bitmap_l0, + MSR_FS_BASE, + MSR_TYPE_W); + if (spec_ctrl) nested_vmx_disable_intercept_for_msr( msr_bitmap_l1, msr_bitmap_l0,