From patchwork Wed Nov 13 12:23:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11241795 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D679013BD for ; Wed, 13 Nov 2019 12:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1780222D0 for ; Wed, 13 Nov 2019 12:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727216AbfKMMX2 (ORCPT ); Wed, 13 Nov 2019 07:23:28 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:16022 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727187AbfKMMX1 (ORCPT ); Wed, 13 Nov 2019 07:23:27 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id xADCIDv1092780 for ; Wed, 13 Nov 2019 07:23:26 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2w8gmhk0ux-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 13 Nov 2019 07:23:26 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 13 Nov 2019 12:23:21 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xADCMirn39256380 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Nov 2019 12:22:44 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C577D4C044; Wed, 13 Nov 2019 12:23:20 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8FDBE4C04A; Wed, 13 Nov 2019 12:23:20 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.152.222.55]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 13 Nov 2019 12:23:20 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH v1 2/4] s390x: Define the PSW bits Date: Wed, 13 Nov 2019 13:23:17 +0100 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1573647799-30584-1-git-send-email-pmorel@linux.ibm.com> References: <1573647799-30584-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19111312-4275-0000-0000-0000037D5F43 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19111312-4276-0000-0000-00003890C0A0 Message-Id: <1573647799-30584-3-git-send-email-pmorel@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-11-13_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=532 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1910280000 definitions=main-1911130116 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Instead of assigning obfuscated masks to the PSW dedicated to the exceptions, let's define the masks explicitely, it will clarify the usage. Signed-off-by: Pierre Morel --- lib/s390x/asm/arch_bits.h | 32 ++++++++++++++++++++++++++++++++ lib/s390x/asm/arch_def.h | 6 ++---- s390x/cstart64.S | 13 +++++++------ 3 files changed, 41 insertions(+), 10 deletions(-) create mode 100644 lib/s390x/asm/arch_bits.h diff --git a/lib/s390x/asm/arch_bits.h b/lib/s390x/asm/arch_bits.h new file mode 100644 index 0000000..0521125 --- /dev/null +++ b/lib/s390x/asm/arch_bits.h @@ -0,0 +1,32 @@ + +/* + * Copyright (c) 2019 IBM Corp + * + * Authors: + * Pierre Morel + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU Library General Public License version 2. + */ +#ifndef _ASM_S390X_ARCH_BITS_H_ +#define _ASM_S390X_ARCH_BITS_H_ + +#define PSW_MASK_PER 0x4000000000000000 +#define PSW_MASK_DAT 0x0400000000000000 +#define PSW_MASK_IO 0x0200000000000000 +#define PSW_MASK_EXT 0x0100000000000000 +#define PSW_MASK_BASE 0x0000000000000000 +#define PSW_MASK_KEY 0x00F0000000000000 +#define PSW_MASK_MCHECK 0x0004000000000000 +#define PSW_MASK_WAIT 0x0002000000000000 +#define PSW_MASK_PSTATE 0x0001000000000000 +#define PSW_MASK_ASC 0x0000C00000000000 +#define PSW_MASK_CC 0x0000300000000000 +#define PSW_MASK_PM 0x00000F0000000000 +#define PSW_MASK_RI 0x0000008000000000 +#define PSW_MASK_EA 0x0000000100000000 +#define PSW_MASK_BA 0x0000000080000000 + +#define PSW_EXCEPTION_MASK (PSW_MASK_EA|PSW_MASK_BA) + +#endif diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 96cca2e..34c1188 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -10,15 +10,13 @@ #ifndef _ASM_S390X_ARCH_DEF_H_ #define _ASM_S390X_ARCH_DEF_H_ +#include + struct psw { uint64_t mask; uint64_t addr; }; -#define PSW_MASK_EXT 0x0100000000000000UL -#define PSW_MASK_DAT 0x0400000000000000UL -#define PSW_MASK_PSTATE 0x0001000000000000UL - #define CR0_EXTM_SCLP 0X0000000000000200UL #define CR0_EXTM_EXTC 0X0000000000002000UL #define CR0_EXTM_EMGC 0X0000000000004000UL diff --git a/s390x/cstart64.S b/s390x/cstart64.S index eaff481..7475f32 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -11,6 +11,7 @@ * under the terms of the GNU Library General Public License version 2. */ #include +#include #include .section .init @@ -196,17 +197,17 @@ svc_int: .align 8 initial_psw: - .quad 0x0000000180000000, clear_bss_start + .quad PSW_EXCEPTION_MASK, clear_bss_start pgm_int_psw: - .quad 0x0000000180000000, pgm_int + .quad PSW_EXCEPTION_MASK, pgm_int ext_int_psw: - .quad 0x0000000180000000, ext_int + .quad PSW_EXCEPTION_MASK, ext_int mcck_int_psw: - .quad 0x0000000180000000, mcck_int + .quad PSW_EXCEPTION_MASK, mcck_int io_int_psw: - .quad 0x0000000180000000, io_int + .quad PSW_EXCEPTION_MASK, io_int svc_int_psw: - .quad 0x0000000180000000, svc_int + .quad PSW_EXCEPTION_MASK, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ .quad 0x0000000000040000