| Message ID | 1597213838-8847-1-git-send-email-wanpengli@tencent.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] KVM: LAPIC: Return 0 when getting the tscdeadline timer if the lapic is hw disabled | expand |
On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote: > From: Wanpeng Li <wanpengli@tencent.com> > > Return 0 when getting the tscdeadline timer if the lapic is hw disabled. It'd be helpful to reference the SDM for the general behavior of the MSR. In other timer modes (LVT bit 18 = 0), the IA32_TSC_DEADLINE MSR reads zero and writes are ignored. I'd also vote to squash the two patches together, they really are paired changes to match the architectural behavior. Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote: > From: Wanpeng Li <wanpengli@tencent.com> > > Return 0 when getting the tscdeadline timer if the lapic is hw disabled. > > Suggested-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > --- Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 5ccbee7..79599af 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2183,8 +2183,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) { struct kvm_lapic *apic = vcpu->arch.apic; - if (!lapic_in_kernel(vcpu) || - !apic_lvtt_tscdeadline(apic)) + if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) return 0; return apic->lapic_timer.tscdeadline;