From patchwork Fri Oct 27 17:00:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reinette Chatre X-Patchwork-Id: 13438648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB76C25B47 for ; Fri, 27 Oct 2023 17:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346406AbjJ0RB6 (ORCPT ); Fri, 27 Oct 2023 13:01:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346209AbjJ0RBl (ORCPT ); Fri, 27 Oct 2023 13:01:41 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77D06D45; Fri, 27 Oct 2023 10:01:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698426097; x=1729962097; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TB0MfEQ6zMbspsfmMyNqxCW0CYXal0biIXEhDTEl/2E=; b=WgdFC9o1ytz2BVQYKAIyoPzCmU4dgwx9DG1tOlA9wcosVysIBK80OVsU UGsAznUUBYcxn9DCTl9TKSSDK8aQ+7OaHdA6lSoeKbYfDIoZXAoJQ1Zdx asZSISlBoad3fQaVd6If8A/vpZ05AyyxzJoF+KAtE+mjkCyG8kxSo4hiy aVSqn3K6nu4s4gB9ELMhoJfsAqXuEdtqknnPYB/uz5++iUj6G9lSGmk1d 3o/rEX/8BvM1vSKzwU+nSaZfpNbsYYtHYfAzDNq37mF2ho+5xhalwZPRN M5LFhbJdmdhY4jf12fhWOFnwq8F1jAdTBLRotDzYfC3LfPi8ZUJUeEfS/ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10876"; a="612019" X-IronPort-AV: E=Sophos;i="6.03,256,1694761200"; d="scan'208";a="612019" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2023 10:01:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10876"; a="1090988211" X-IronPort-AV: E=Sophos;i="6.03,256,1694761200"; d="scan'208";a="1090988211" Received: from rchatre-ws.ostc.intel.com ([10.54.69.144]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2023 10:01:18 -0700 From: Reinette Chatre To: jgg@nvidia.com, yishaih@nvidia.com, shameerali.kolothum.thodi@huawei.com, kevin.tian@intel.com, alex.williamson@redhat.com Cc: kvm@vger.kernel.org, dave.jiang@intel.com, jing2.liu@intel.com, ashok.raj@intel.com, fenghua.yu@intel.com, tom.zanussi@linux.intel.com, reinette.chatre@intel.com, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [RFC PATCH V3 17/26] vfio/pci: Make vfio_pci_set_irqs_ioctl() available Date: Fri, 27 Oct 2023 10:00:49 -0700 Message-Id: <1b51730bac31a6f491ef44b722f0bd19da4312dc.1698422237.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org vfio_pci_set_irqs_ioctl() is now a generic entrypoint that can be configured to support different interrupt management backend. Export vfio_pci_set_irqs_ioctl() for use by other virtual device drivers. Signed-off-by: Reinette Chatre --- Changes since RFC V2: - Improve changelog. drivers/vfio/pci/vfio_pci_intrs.c | 1 + include/linux/vfio_pci_core.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c index 14131d5288e3..80040fde6f6b 100644 --- a/drivers/vfio/pci/vfio_pci_intrs.c +++ b/drivers/vfio/pci/vfio_pci_intrs.c @@ -916,3 +916,4 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_intr_ctx *intr_ctx, uint32_t flags, mutex_unlock(&intr_ctx->igate); return ret; } +EXPORT_SYMBOL_GPL(vfio_pci_set_irqs_ioctl); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index e666c19da223..8d2fb51a2dcc 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -158,6 +158,9 @@ long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd, void vfio_pci_init_intr_ctx(struct vfio_pci_core_device *vdev, struct vfio_pci_intr_ctx *intr_ctx); void vfio_pci_release_intr_ctx(struct vfio_pci_intr_ctx *intr_ctx); +int vfio_pci_set_irqs_ioctl(struct vfio_pci_intr_ctx *intr_ctx, uint32_t flags, + unsigned int index, unsigned int start, + unsigned int count, void *data); int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, void __user *arg, size_t argsz); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf,