From patchwork Fri May 15 13:19:43 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 24088 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4FDLmN3010619 for ; Fri, 15 May 2009 13:21:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763020AbZEONT5 (ORCPT ); Fri, 15 May 2009 09:19:57 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1760546AbZEONT4 (ORCPT ); Fri, 15 May 2009 09:19:56 -0400 Received: from outbound-dub.frontbridge.com ([213.199.154.16]:53614 "EHLO IE1EHSOBE004.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763024AbZEONTz convert rfc822-to-8bit (ORCPT ); Fri, 15 May 2009 09:19:55 -0400 Received: from mail72-dub-R.bigfish.com (10.5.252.3) by IE1EHSOBE004.bigfish.com (10.5.252.24) with Microsoft SMTP Server id 8.1.340.0; Fri, 15 May 2009 13:19:56 +0000 Received: from mail72-dub (localhost.localdomain [127.0.0.1]) by mail72-dub-R.bigfish.com (Postfix) with ESMTP id 3440917100F0; Fri, 15 May 2009 13:19:56 +0000 (UTC) X-BigFish: VPS-33(zz146fK1432R98dR936eN1805M936fJzz1202hzzz32i6bh43j61h) X-Spam-TCS-SCL: 0:0 Received: by mail72-dub (MessageSwitch) id 124239359513933_31291; Fri, 15 May 2009 13:19:55 +0000 (UCT) Received: from svlb1extmailp02.amd.com (unknown [139.95.251.11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail72-dub.bigfish.com (Postfix) with ESMTP id 5F7C110F0058; Fri, 15 May 2009 13:19:53 +0000 (UTC) Received: from svlb1twp02.amd.com ([139.95.250.35]) by svlb1extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n4FDJjFh014672; Fri, 15 May 2009 06:19:48 -0700 X-WSS-ID: 0KJOT0T-04-JC5-01 Received: from SSVLEXBH1.amd.com (ssvlexbh1.amd.com [139.95.53.182]) by svlb1twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 23D291103C0; Fri, 15 May 2009 06:19:41 -0700 (PDT) Received: from ssvlexmb2.amd.com ([139.95.53.7]) by SSVLEXBH1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 May 2009 06:19:47 -0700 Received: from SF36EXMB1.amd.com ([172.19.4.24]) by ssvlexmb2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 May 2009 06:19:47 -0700 Received: from seurexmb1.amd.com ([165.204.82.130]) by SF36EXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 May 2009 15:19:43 +0200 Received: from lemmy.amd.com ([165.204.15.93]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 May 2009 15:19:43 +0200 Received: by lemmy.amd.com (Postfix, from userid 41430) id 3F344C9B94; Fri, 15 May 2009 15:19:43 +0200 (CEST) Date: Fri, 15 May 2009 15:19:43 +0200 From: Joerg Roedel To: Alexander Graf CC: "Michael S. Tsirkin" , kvm@vger.kernel.org Subject: Re: [PATCH 2/6] MMU: don't bail on PAT bits in PTE Message-ID: <20090515131943.GT9835@amd.com> References: <1242375740-31222-1-git-send-email-agraf@suse.de> <1242375740-31222-2-git-send-email-agraf@suse.de> <1242375740-31222-3-git-send-email-agraf@suse.de> <20090515102507.GA4933@redhat.com> <44CC74E2-96C3-45C6-9412-A252A53C966A@suse.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <44CC74E2-96C3-45C6-9412-A252A53C966A@suse.de> User-Agent: Mutt/1.5.18 (2008-05-17) X-OriginalArrivalTime: 15 May 2009 13:19:43.0546 (UTC) FILETIME=[CF6DD1A0:01C9D55F] Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, May 15, 2009 at 12:53:42PM +0200, Alexander Graf wrote: > > On 15.05.2009, at 12:25, Michael S. Tsirkin wrote: > >> On Fri, May 15, 2009 at 10:22:16AM +0200, Alexander Graf wrote: >>> A 64bit PTE can have bit7 set to 1 which means "Use this bit for the >>> PAT". >>> Currently KVM's MMU code treats this bit as reserved, even though >>> it's not. >>> >>> As long as we're not required to make use of the PAT bits which is >>> only >>> required for DMA/MMIO from my understanding, we can safely ignore it. >>> >>> Hyper-V uses this bit for kernel PTEs. >>> >>> Signed-off-by: Alexander Graf >>> --- >>> arch/x86/kvm/mmu.c | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c >>> index 8fcdae9..cce055a 100644 >>> --- a/arch/x86/kvm/mmu.c >>> +++ b/arch/x86/kvm/mmu.c >>> @@ -2169,7 +2169,7 @@ static void reset_rsvds_bits_mask(struct >>> kvm_vcpu *vcpu, int level) >>> context->rsvd_bits_mask[1][1] = exb_bit_rsvd | >>> rsvd_bits(maxphyaddr, 51) | >>> rsvd_bits(13, 20); /* large page */ >>> - context->rsvd_bits_mask[1][0] = ~0ull; >>> + context->rsvd_bits_mask[1][0] = 0ull; >>> break; >>> } >>> } >> >> Just to make sure I understand what this does: if guest sets bit7, >> will >> bit7 get set in shadow PTEs as well? > > I don't see any code that interprets bit7, so the shadow PTE should be > completely unaffected. > > But to be sure I asked Jörg to take a look at it as well, as he's more > familiar with the x86 SPT code than I am :-). The PAT bit is not propagated into the shadow page tables. Anyway, the problem is fixed the wrong way in this patch. The real problem is that a 4kb pte is checked with mask considered for large pages (which do not exist on walker level 0). The attached patch fixes it the better way imho. From 7530aef3ed580b70a74224f8c04857754501c496 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Fri, 15 May 2009 15:14:19 +0200 Subject: [PATCH] kvm/mmu: fix reserved bit checking on 4kb pte level The reserved bits checking code looks at bit 7 of the pte to determine if it has to use the mask for a large pte or a normal pde. This does not work on 4kb pte level because bit 7 is used there for PAT. Account this in the checking function. Signed-off-by: Joerg Roedel --- arch/x86/kvm/mmu.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 479e748..8d9552e 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2124,9 +2124,11 @@ static void paging_free(struct kvm_vcpu *vcpu) static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) { - int bit7; + int bit7 = 0; + + if (level != PT_PAGE_TABLE_LEVEL) + bit7 = (gpte >> 7) & 1; - bit7 = (gpte >> 7) & 1; return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; }