From patchwork Sun Oct 17 10:16:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nadav Har'El X-Patchwork-Id: 259961 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o9HAGTZV020391 for ; Sun, 17 Oct 2010 10:16:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932412Ab0JQKQ1 (ORCPT ); Sun, 17 Oct 2010 06:16:27 -0400 Received: from mtagate6.uk.ibm.com ([194.196.100.166]:56169 "EHLO mtagate6.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932389Ab0JQKQ1 (ORCPT ); Sun, 17 Oct 2010 06:16:27 -0400 Received: from d06nrmr1806.portsmouth.uk.ibm.com (d06nrmr1806.portsmouth.uk.ibm.com [9.149.39.193]) by mtagate6.uk.ibm.com (8.13.1/8.13.1) with ESMTP id o9HAGQQ1011988 for ; Sun, 17 Oct 2010 10:16:26 GMT Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by d06nrmr1806.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o9HAGQrX3412022 for ; Sun, 17 Oct 2010 11:16:26 +0100 Received: from d06av07.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id o9HAGPpb007711 for ; Sun, 17 Oct 2010 04:16:25 -0600 Received: from rice.haifa.ibm.com (rice.haifa.ibm.com [9.148.8.112]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id o9HAGOkk007708 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 17 Oct 2010 04:16:25 -0600 Received: from rice.haifa.ibm.com (lnx-nyh.haifa.ibm.com [127.0.0.1]) by rice.haifa.ibm.com (8.14.4/8.14.4) with ESMTP id o9HAGNC6029619; Sun, 17 Oct 2010 12:16:24 +0200 Received: (from nyh@localhost) by rice.haifa.ibm.com (8.14.4/8.14.4/Submit) id o9HAGNRw029617; Sun, 17 Oct 2010 12:16:23 +0200 Date: Sun, 17 Oct 2010 12:16:23 +0200 Message-Id: <201010171016.o9HAGNRw029617@rice.haifa.ibm.com> X-Authentication-Warning: rice.haifa.ibm.com: nyh set sender to "Nadav Har'El" using -f Cc: gleb@redhat.com, avi@redhat.com To: kvm@vger.kernel.org From: "Nadav Har'El" References: <1287309814-nyh@il.ibm.com> Subject: [PATCH 25/27] nVMX: Additional TSC-offset handling Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sun, 17 Oct 2010 10:16:30 +0000 (UTC) --- .before/arch/x86/kvm/vmx.c 2010-10-17 11:52:03.000000000 +0200 +++ .after/arch/x86/kvm/vmx.c 2010-10-17 11:52:03.000000000 +0200 @@ -1674,12 +1674,23 @@ static u64 guest_read_tsc(void) static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) { vmcs_write64(TSC_OFFSET, offset); + if (to_vmx(vcpu)->nested.nested_mode) + /* + * We are only changing TSC_OFFSET when L2 is running if for + * some reason L1 chose not to trap the TSC MSR. Since + * prepare_vmcs12() does not copy tsc_offset, we need to also + * set the vmcs12 field here. + */ + get_vmcs12_fields(vcpu)->tsc_offset = offset - + to_vmx(vcpu)->nested.vmcs01_fields->tsc_offset; } static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) { u64 offset = vmcs_read64(TSC_OFFSET); vmcs_write64(TSC_OFFSET, offset + adjustment); + if (to_vmx(vcpu)->nested.nested_mode) + get_vmcs12_fields(vcpu)->tsc_offset += adjustment; } /*