From patchwork Wed Dec 8 17:13:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nadav Har'El X-Patchwork-Id: 391292 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB8HDOXp020830 for ; Wed, 8 Dec 2010 17:13:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753853Ab0LHRNV (ORCPT ); Wed, 8 Dec 2010 12:13:21 -0500 Received: from mtagate3.uk.ibm.com ([194.196.100.163]:35551 "EHLO mtagate3.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751676Ab0LHRNU (ORCPT ); Wed, 8 Dec 2010 12:13:20 -0500 Received: from d06nrmr1707.portsmouth.uk.ibm.com (d06nrmr1707.portsmouth.uk.ibm.com [9.149.39.225]) by mtagate3.uk.ibm.com (8.13.1/8.13.1) with ESMTP id oB8HDJ2t012329 for ; Wed, 8 Dec 2010 17:13:19 GMT Received: from d06av06.portsmouth.uk.ibm.com (d06av06.portsmouth.uk.ibm.com [9.149.37.217]) by d06nrmr1707.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id oB8HDKpc3424484 for ; Wed, 8 Dec 2010 17:13:20 GMT Received: from d06av06.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av06.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id oB8HDIJv023613 for ; Wed, 8 Dec 2010 10:13:19 -0700 Received: from rice.haifa.ibm.com (rice.haifa.ibm.com [9.148.8.217]) by d06av06.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id oB8HDIJf023599 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 8 Dec 2010 10:13:18 -0700 Received: from rice.haifa.ibm.com (lnx-nyh.haifa.ibm.com [127.0.0.1]) by rice.haifa.ibm.com (8.14.4/8.14.4) with ESMTP id oB8HDHle008837; Wed, 8 Dec 2010 19:13:17 +0200 Received: (from nyh@localhost) by rice.haifa.ibm.com (8.14.4/8.14.4/Submit) id oB8HDHkL008835; Wed, 8 Dec 2010 19:13:17 +0200 Date: Wed, 8 Dec 2010 19:13:17 +0200 Message-Id: <201012081713.oB8HDHkL008835@rice.haifa.ibm.com> X-Authentication-Warning: rice.haifa.ibm.com: nyh set sender to "Nadav Har'El" using -f Cc: gleb@redhat.com, avi@redhat.com To: kvm@vger.kernel.org From: "Nadav Har'El" References: <1291827596-nyh@il.ibm.com> Subject: [PATCH 26/28] nVMX: Additional TSC-offset handling Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 08 Dec 2010 17:13:25 +0000 (UTC) --- .before/arch/x86/kvm/vmx.c 2010-12-08 18:56:52.000000000 +0200 +++ .after/arch/x86/kvm/vmx.c 2010-12-08 18:56:52.000000000 +0200 @@ -1665,12 +1665,23 @@ static u64 guest_read_tsc(void) static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) { vmcs_write64(TSC_OFFSET, offset); + if (is_guest_mode(vcpu)) + /* + * We are only changing TSC_OFFSET when L2 is running if for + * some reason L1 chose not to trap the TSC MSR. Since + * prepare_vmcs12() does not copy tsc_offset, we need to also + * set the vmcs12 field here. + */ + get_vmcs12_fields(vcpu)->tsc_offset = offset - + to_vmx(vcpu)->nested.vmcs01_fields->tsc_offset; } static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) { u64 offset = vmcs_read64(TSC_OFFSET); vmcs_write64(TSC_OFFSET, offset + adjustment); + if (is_guest_mode(vcpu)) + get_vmcs12_fields(vcpu)->tsc_offset += adjustment; } /*