From patchwork Thu Aug 16 15:28:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1333501 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 687F7E0000 for ; Thu, 16 Aug 2012 15:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964867Ab2HPP2q (ORCPT ); Thu, 16 Aug 2012 11:28:46 -0400 Received: from mail-qa0-f46.google.com ([209.85.216.46]:42299 "EHLO mail-qa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964860Ab2HPP2o (ORCPT ); Thu, 16 Aug 2012 11:28:44 -0400 Received: by mail-qa0-f46.google.com with SMTP id s11so661176qaa.19 for ; Thu, 16 Aug 2012 08:28:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:date:message-id:in-reply-to:references:user-agent :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=catPoj0O6nX3UoGwq9n5Dt12qMWPubmcwLWpfw+2Gc8=; b=cZ8ndST7FipxH2+DlOf/YleFmFF6HPvRT8OdN8+dt26TXNzoxltN5pSeJkMoew0Jaj R0BzXCyK+LEJey7YqVR5NcjNYB4pDx2LL10MJxQiOwzb2uZYKA0cKxqL7xBcYzxM3vaU cPymeUK68+cpQ+enxX+GOnpnSDCCmVgUm7gfmb/1IQQRTjyP/CUH/mQ6nr2tyi9SXQXK L8Bd/XaSZspMkH0GcOfJPWfg4GJr+NezeqKblsTITRmgnppeLp223lxtwbca7KAkocIu p+ITT3AaHup9DW17I2pVXCczKpVD45wpbtL62nIteiJAIikxeK77i48dZ5Ikw2aegCSn TeoA== Received: by 10.224.203.197 with SMTP id fj5mr3800006qab.98.1345130924414; Thu, 16 Aug 2012 08:28:44 -0700 (PDT) Received: from [127.0.1.1] (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id co12sm6985602qab.20.2012.08.16.08.28.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 16 Aug 2012 08:28:43 -0700 (PDT) Subject: [PATCH v10 04/14] ARM: Expose PMNC bitfields for KVM use To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org From: Christoffer Dall Date: Thu, 16 Aug 2012 11:28:42 -0400 Message-ID: <20120816152842.21484.79439.stgit@ubuntu> In-Reply-To: <20120816152637.21484.65421.stgit@ubuntu> References: <20120816152637.21484.65421.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkAuycNylOUZIslp2bsc8IY6GDkoAysLk/+rNNVaoKzt3fDu1FHdrxC1AYe2SMKDcJimGX8 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Rusty Russell We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h. Signed-off-by: Rusty Russell --- arch/arm/include/asm/perf_bits.h | 56 ++++++++++++++++++++++++++++++++++++++ arch/arm/kernel/perf_event_v7.c | 51 +---------------------------------- 2 files changed, 57 insertions(+), 50 deletions(-) create mode 100644 arch/arm/include/asm/perf_bits.h -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/include/asm/perf_bits.h b/arch/arm/include/asm/perf_bits.h new file mode 100644 index 0000000..eeb266a --- /dev/null +++ b/arch/arm/include/asm/perf_bits.h @@ -0,0 +1,56 @@ +#ifndef __ARM_PERF_BITS_H__ +#define __ARM_PERF_BITS_H__ + +/* + * ARMv7 low level PMNC access + */ + +/* + * Per-CPU PMNC: config reg + */ +#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ +#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ +#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ +#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ +#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ +#define ARMV7_PMNC_N_MASK 0x1f +#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ + +/* + * FLAG: counters overflow flag status reg + */ +#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */ +#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv2 + */ +#define ARMV7_EXCLUDE_PL1 (1 << 31) +#define ARMV7_EXCLUDE_USER (1 << 30) +#define ARMV7_INCLUDE_HYP (1 << 27) + +#ifndef __ASSEMBLY__ +static inline u32 armv7_pmnc_read(void) +{ + u32 val; + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); + return val; +} + +static inline void armv7_pmnc_write(u32 val) +{ + val &= ARMV7_PMNC_MASK; + isb(); + asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); +} +#endif + +#endif /* __ARM_PERF_BITS_H__ */ diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index f04070b..09851b3 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -17,6 +17,7 @@ */ #ifdef CONFIG_CPU_V7 +#include static struct arm_pmu armv7pmu; @@ -744,61 +745,11 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) /* - * ARMv7 low level PMNC access - */ - -/* * Perf Event to low level counters mapping */ #define ARMV7_IDX_TO_COUNTER(x) \ (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) -/* - * Per-CPU PMNC: config reg - */ -#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ -#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ -#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ -#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ -#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ -#define ARMV7_PMNC_N_MASK 0x1f -#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ - -/* - * FLAG: counters overflow flag status reg - */ -#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */ -#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv2 - */ -#define ARMV7_EXCLUDE_PL1 (1 << 31) -#define ARMV7_EXCLUDE_USER (1 << 30) -#define ARMV7_INCLUDE_HYP (1 << 27) - -static inline u32 armv7_pmnc_read(void) -{ - u32 val; - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); - return val; -} - -static inline void armv7_pmnc_write(u32 val) -{ - val &= ARMV7_PMNC_MASK; - isb(); - asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); -} - static inline int armv7_pmnc_has_overflowed(u32 pmnc) { return pmnc & ARMV7_OVERFLOWED_MASK;