From patchwork Mon Oct 1 09:10:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1529921 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 0E42E3FE1C for ; Mon, 1 Oct 2012 09:10:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752518Ab2JAJK2 (ORCPT ); Mon, 1 Oct 2012 05:10:28 -0400 Received: from mail-qa0-f53.google.com ([209.85.216.53]:49258 "EHLO mail-qa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752445Ab2JAJKX (ORCPT ); Mon, 1 Oct 2012 05:10:23 -0400 Received: by qaas11 with SMTP id s11so1339638qaa.19 for ; Mon, 01 Oct 2012 02:10:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:date:message-id:in-reply-to:references:user-agent :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=cM6mHTvsH9zP0IbIfEuIkO/5crYdHEK8acMXwvQtu5Q=; b=GkrHRzS+d57fD3y2yhdvH7phicjAfl3z9rSLw7KjXz3EycKTktnDllYZ4TYirJY2B9 A/T2AXy4RsHGenm8vjmA+KgYe7DnsJX1qGoqV7HisV0f8eAxAvBFaJ8pVHmTajXFyAdI MszXn0AmjIxTNHRBB4iTjg8RPzBhFgcOX/zQTq0uOpuBF/w9jeu2CsQbRu5qeTKcIVOL JDdHoEgtOpdenBYfbBpe8LYyTGhJZ1EIA/xzEmNDSff0fMLcD/35h5P8MmLKs67cMb71 U1Vyn2AEsUKD1shNk9jmwKOsCiUCi6FMyTioI06QiuCWT3cgCElL2PjZKVXnGm0zPwAA v41Q== Received: by 10.229.135.10 with SMTP id l10mr9683183qct.37.1349082622614; Mon, 01 Oct 2012 02:10:22 -0700 (PDT) Received: from [127.0.1.1] (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id b5sm23779784qao.13.2012.10.01.02.10.21 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Oct 2012 02:10:22 -0700 (PDT) Subject: [PATCH v2 03/14] ARM: Factor out cpuid implementor and part number To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu From: Christoffer Dall Date: Mon, 01 Oct 2012 05:10:20 -0400 Message-ID: <20121001091020.49198.94718.stgit@ubuntu> In-Reply-To: <20121001090945.49198.68950.stgit@ubuntu> References: <20121001090945.49198.68950.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkc1K0+7jcOlTEkr6BjsBdVoTewFL5kaALE6a7SxZdXZ2cNhSCrIldO10PVvXYmBNnFJIN1 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Decoding the implementor and part number of the CPU id in the CPU ID register is needed by KVM, so we factor it out to share the code. Signed-off-by: Christoffer Dall --- arch/arm/include/asm/cputype.h | 26 ++++++++++++++++++++++++++ arch/arm/kernel/perf_event.c | 30 +++++++++++++++--------------- 2 files changed, 41 insertions(+), 15 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb47d28..306fb2c 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -51,6 +51,22 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define IMPLEMENTOR_ARM 0x41 +#define IMPLEMENTOR_INTEL 0x69 + +#define PART_NUMBER_ARM1136 0xB360 +#define PART_NUMBER_ARM1156 0xB560 +#define PART_NUMBER_ARM1176 0xB760 +#define PART_NUMBER_ARM11MPCORE 0xB020 +#define PART_NUMBER_CORTEX_A8 0xC080 +#define PART_NUMBER_CORTEX_A9 0xC090 +#define PART_NUMBER_CORTEX_A5 0xC050 +#define PART_NUMBER_CORTEX_A15 0xC0F0 +#define PART_NUMBER_CORTEX_A7 0xC070 + +#define PART_NUMBER_XSCALE1 0x1 +#define PART_NUMBER_XSCALE2 0x2 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -61,6 +77,16 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return (read_cpuid_id() & 0xFFF0); +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index ab243b8..c8243c6 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -709,44 +709,44 @@ static int __init init_hw_perf_events(void) { unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == IMPLEMENTOR_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case PART_NUMBER_ARM1136: + case PART_NUMBER_ARM1156: + case PART_NUMBER_ARM1176: cpu_pmu = armv6pmu_init(); break; - case 0xB020: /* ARM11mpcore */ + case PART_NUMBER_ARM11MPCORE: cpu_pmu = armv6mpcore_pmu_init(); break; - case 0xC080: /* Cortex-A8 */ + case PART_NUMBER_CORTEX_A8: cpu_pmu = armv7_a8_pmu_init(); break; - case 0xC090: /* Cortex-A9 */ + case PART_NUMBER_CORTEX_A9: cpu_pmu = armv7_a9_pmu_init(); break; - case 0xC050: /* Cortex-A5 */ + case PART_NUMBER_CORTEX_A5: cpu_pmu = armv7_a5_pmu_init(); break; - case 0xC0F0: /* Cortex-A15 */ + case PART_NUMBER_CORTEX_A15: cpu_pmu = armv7_a15_pmu_init(); break; - case 0xC070: /* Cortex-A7 */ + case PART_NUMBER_CORTEX_A7: cpu_pmu = armv7_a7_pmu_init(); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { + } else if (implementor == IMPLEMENTOR_INTEL) { part_number = (cpuid >> 13) & 0x7; switch (part_number) { - case 1: + case PART_NUMBER_XSCALE1: cpu_pmu = xscale1pmu_init(); break; - case 2: + case PART_NUMBER_XSCALE2: cpu_pmu = xscale2pmu_init(); break; }