@@ -259,7 +259,7 @@ int kvm_arch_get_registers(CPUState *cpu);
int kvm_arch_put_registers(CPUState *cpu, int level);
-int kvm_arch_init(KVMState *s);
+int kvm_arch_init(MachineState *ms, KVMState *s);
int kvm_arch_init_vcpu(CPUState *cpu);
@@ -1598,7 +1598,7 @@ static int kvm_init(MachineState *ms)
kvm_resamplefds_allowed =
(kvm_check_extension(s, KVM_CAP_IRQFD_RESAMPLE) > 0);
- ret = kvm_arch_init(s);
+ ret = kvm_arch_init(ms, s);
if (ret < 0) {
goto err;
}
@@ -150,7 +150,7 @@ static const TypeInfo host_arm_cpu_type_info = {
.class_size = sizeof(ARMHostCPUClass),
};
-int kvm_arch_init(KVMState *s)
+int kvm_arch_init(MachineState *ms, KVMState *s)
{
/* For ARM interrupt delivery is always asynchronous,
* whether we are using an in-kernel VGIC or not.
@@ -840,7 +840,7 @@ static int kvm_get_supported_msrs(KVMState *s)
return ret;
}
-int kvm_arch_init(KVMState *s)
+int kvm_arch_init(MachineState *ms, KVMState *s)
{
uint64_t identity_base = 0xfffbc000;
uint64_t shadow_mem;
@@ -40,7 +40,7 @@ unsigned long kvm_arch_vcpu_id(CPUState *cs)
return cs->cpu_index;
}
-int kvm_arch_init(KVMState *s)
+int kvm_arch_init(MachineState *ms, KVMState *s)
{
/* MIPS has 128 signals */
kvm_set_sigmask_len(s, 16);
@@ -95,7 +95,7 @@ static void kvm_kick_cpu(void *opaque)
static int kvm_ppc_register_host_cpu_type(void);
-int kvm_arch_init(KVMState *s)
+int kvm_arch_init(MachineState *ms, KVMState *s)
{
cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
@@ -173,7 +173,7 @@ static void kvm_s390_enable_cmma(KVMState *s)
trace_kvm_enable_cmma(rc);
}
-int kvm_arch_init(KVMState *s)
+int kvm_arch_init(MachineState *ms, KVMState *s)
{
cap_sync_regs = kvm_check_extension(s, KVM_CAP_SYNC_REGS);
cap_async_pf = kvm_check_extension(s, KVM_CAP_ASYNC_PF);