From patchwork Fri Jun 3 06:09:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9151871 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1BB4560221 for ; Fri, 3 Jun 2016 06:10:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E53A9281F9 for ; Fri, 3 Jun 2016 06:10:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D92FD28309; Fri, 3 Jun 2016 06:10:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F880281F9 for ; Fri, 3 Jun 2016 06:10:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751882AbcFCGKh (ORCPT ); Fri, 3 Jun 2016 02:10:37 -0400 Received: from mga04.intel.com ([192.55.52.120]:18804 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbcFCGKg (ORCPT ); Fri, 3 Jun 2016 02:10:36 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 02 Jun 2016 23:10:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,410,1459839600"; d="scan'208";a="990185178" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.126]) by orsmga002.jf.intel.com with ESMTP; 02 Jun 2016 23:10:32 -0700 From: Haozhong Zhang To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcelo Tosatti , "Michael S . Tsirkin" , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , Ashok Raj , Haozhong Zhang Subject: [PATCH v3 2/2] target-i386: add migration support for Intel LMCE Date: Fri, 3 Jun 2016 14:09:44 +0800 Message-Id: <20160603060944.17373-3-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160603060944.17373-1-haozhong.zhang@intel.com> References: <20160603060944.17373-1-haozhong.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP LMCE is disabled by default, but a cpu option 'lmce=on/off' is provided to enable/disable it. Migration is only allowed between VCPUs with the same lmce option. Signed-off-by: Haozhong Zhang --- Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Boris Petkov Cc: Tony Luck Cc: Andi Kleen Cc: Ashok Raj --- include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 1 + target-i386/cpu.h | 5 +++++ target-i386/machine.c | 24 ++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ca23609..058eef9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -357,7 +357,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 + HW_COMPAT_2_6 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "lmce",\ + .value = "off",\ + }, #define PC_COMPAT_2_5 \ PC_COMPAT_2_6 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9b4dbab..c69cc17 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3232,6 +3232,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), + DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_END_OF_LIST() }; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2d411ba..b512fd6 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1182,6 +1182,11 @@ struct X86CPU { */ bool enable_pmu; + /* Enable LMCE support which is set via cpu option 'lmce=on/off'. LMCE is + * disabled by default to avoid breaking the migration between QEMU with + * different LMCE support. Only migrating between QEMU with the same LMCE + * support is allowed. + */ bool enable_lmce; /* in order to simplify APIC support, we leave this pointer to the diff --git a/target-i386/machine.c b/target-i386/machine.c index cb9adf2..b55d376 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -347,6 +347,11 @@ static int cpu_post_load(void *opaque, int version_id) return -EINVAL; } + if (!cpu->enable_lmce && (env->mcg_cap & MCG_LMCE_P)) { + error_report("LMCE not enabled"); + return -EINVAL; + } + /* * Real mode guest segments register DPL should be zero. * Older KVM version were setting it wrongly. @@ -896,6 +901,24 @@ static const VMStateDescription vmstate_tsc_khz = { } }; +static bool mcg_ext_ctl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + return cpu->enable_lmce && env->mcg_ext_ctl; +} + +static const VMStateDescription vmstate_mcg_ext_ctl = { + .name = "cpu/mcg_ext_ctl", + .version_id = 1, + .minimum_version_id = 1, + .needed = mcg_ext_ctl_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -1022,6 +1045,7 @@ VMStateDescription vmstate_x86_cpu = { #ifdef TARGET_X86_64 &vmstate_pkru, #endif + &vmstate_mcg_ext_ctl, NULL } };