From patchwork Thu Nov 10 23:40:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyle Huey X-Patchwork-Id: 9422219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2D05560720 for ; Thu, 10 Nov 2016 23:41:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D68E29858 for ; Thu, 10 Nov 2016 23:41:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11D132985B; Thu, 10 Nov 2016 23:41:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A440129858 for ; Thu, 10 Nov 2016 23:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964815AbcKJXlr (ORCPT ); Thu, 10 Nov 2016 18:41:47 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36336 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936211AbcKJXlQ (ORCPT ); Thu, 10 Nov 2016 18:41:16 -0500 Received: by mail-pf0-f195.google.com with SMTP id n85so96813pfi.3 for ; Thu, 10 Nov 2016 15:41:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kylehuey.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VOUSiRm4tYUc9wCdLWJbogZ0eT+iiRPl5uKPkyNxJBo=; b=hIJqAaTG8vE+88CEFxqQQB81K5n5bYSGDN+yfc+IY5FrDdCixf0EHxYzFQizuiEp9V MaIh41ed+WPMf1feiqzkW4uZ9+//OSs9G9BHEwET7ptoKderWfqeMrCG7dMHb4UseW7a iY2PXKf1H8MpkUtTMmiIhTK2s+psXdL61vLyiZwhoRVu2R5XTiVNU1tm+ut3kwkAFdQQ XqW1ivdcop4WZCbYyJDHZx4EDA5y9rGMegS2ZrJBNIfKTrPshUFB8XB+qzkMxa/hoLlP fu/adLNEhGi46ytnD8nZZLkpgRz1XOd3b/BahRoMra+0570SJH4R/dMCmVQIX7dCd0/Y VH3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VOUSiRm4tYUc9wCdLWJbogZ0eT+iiRPl5uKPkyNxJBo=; b=fEt6cK/TSuJg3YLikxwxPIkGaW57rJH3hYQ4SzkBTpsG0jK/TBI7k3SevKo61kBDUD EhYpyJyq4Ddo2jBhtngUsxLuK5k/q1hioJ2vWWi+Y8acQOHPcYRsObOGNf2pyP2JXmM/ NIbT/QakQaSGETA/65I2P3zcz+rk3JewMSExDDsamlObdG8HCP9ip98/1OAs1AwZ7xZh QCPjGwJhR4d2VtIR435PtonXuj1CU+GmLSMaxoDpB5CA0ugfwBQ1d75d9ol/wjdtqiql 7VbcpPAWZh5DQHOGzH5+FFhZl9ZO//ocQCVn5tQ5W/7b7xlCNpfC6Lg2pJ88fTM/1I1x knQQ== X-Gm-Message-State: ABUngveXnxn+YH9jY4WiQyjF1Eqk0EmNNf+kNogdaDAdIVqNAsBdYKcgRNqJWL/2YlX/vw== X-Received: by 10.99.251.5 with SMTP id o5mr27687998pgh.160.1478821275493; Thu, 10 Nov 2016 15:41:15 -0800 (PST) Received: from minbar.hsd1.ca.comcast.net (c-73-162-102-141.hsd1.ca.comcast.net. [73.162.102.141]) by smtp.gmail.com with ESMTPSA id z6sm9789779pay.31.2016.11.10.15.41.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 15:41:14 -0800 (PST) From: Kyle Huey X-Google-Original-From: Kyle Huey To: Robert O'Callahan , Thomas Gleixner , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , David Matlack Cc: linux-kernel@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, linux-fsdevel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH v11 5/7] x86/cpufeature: Detect CPUID faulting support Date: Thu, 10 Nov 2016 15:40:53 -0800 Message-Id: <20161110234055.8654-6-khuey@kylehuey.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161110234055.8654-1-khuey@kylehuey.com> References: <20161110234055.8654-1-khuey@kylehuey.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Intel supports faulting on the CPUID instruction beginning with Ivy Bridge. When enabled, the processor will fault on attempts to execute the CPUID instruction with CPL>0. This will allow a ptracer to emulate the CPUID instruction. Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is documented in detail in Section 2.3.2 of https://bugzilla.kernel.org/attachment.cgi?id=243991 Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT. Signed-off-by: Kyle Huey --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/intel.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index a396292..85f853f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -182,16 +182,17 @@ /* * Auxiliary flags: Linux defined - For features scattered in various * CPUID levels like 0x6, 0xA etc, word 7. * * Reuse free bits when adding new feature flags! */ +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 0) /* Intel CPUID faulting */ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 78f3760..3ac0acf 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -36,16 +36,18 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce +#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 +#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fcd484d..19b56b5 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -447,16 +447,26 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c) { /* * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, * so reinitialize it properly like during bootup: */ init_intel_energy_perf(c); } +static void init_intel_misc_features_enables(struct cpuinfo_x86 *c) +{ + u64 msr; + + if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { + if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) + set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); + } +} + static void init_intel(struct cpuinfo_x86 *c) { unsigned int l2 = 0; early_init_intel(c); intel_workarounds(c); @@ -560,16 +570,18 @@ static void init_intel(struct cpuinfo_x86 *c) /* Work around errata */ srat_detect_node(c); if (cpu_has(c, X86_FEATURE_VMX)) detect_vmx_virtcap(c); init_intel_energy_perf(c); + + init_intel_misc_features_enables(c); } #ifdef CONFIG_X86_32 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) { /* * Intel PIII Tualatin. This comes in two flavours. * One has 256kb of cache, the other 512. We have no way