From patchwork Thu Dec 29 22:43:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9491649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DEBF060453 for ; Thu, 29 Dec 2016 22:44:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC2CA1FF15 for ; Thu, 29 Dec 2016 22:44:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C0AB025D9E; Thu, 29 Dec 2016 22:44:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8A111FF15 for ; Thu, 29 Dec 2016 22:44:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753199AbcL2Wnv (ORCPT ); Thu, 29 Dec 2016 17:43:51 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46514 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753039AbcL2Wnt (ORCPT ); Thu, 29 Dec 2016 17:43:49 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AC12061406; Thu, 29 Dec 2016 22:43:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051428; bh=5sJuCisHP4XqjoN6qFRx7TdYuFSTomspNu/mCI8BCHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UR9H7XaCdm+Qr5uAkZib4x9rPKPXPDAinwWdjzNCfg/4oHv07XJtsbXkVoJ/SXdrT pGnQhpZBjGne6GP9kubBNKkvkSUkvQtTY85V86ibwp7GgicNck6y8pGAALGhanuLXq 0l6ni3oS2fJg3Q/VQGOo3fhB3Y3Fu9WG7nNn/4rY= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6CA836115D; Thu, 29 Dec 2016 22:43:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051427; bh=5sJuCisHP4XqjoN6qFRx7TdYuFSTomspNu/mCI8BCHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WIPhVvEZ43iKDrbZ2g7MzTfawwhgOC7irPCTdFwRReRZZ1f5RNs5w54OKLwdBhqA5 xDfC+UkXGsjX7SboVkwjU0qr/NqAaaWjPUMxT6OLxp8BMGZ1pP/5qz9BcoUDxOVNQ6 QZ/eUoB3RWtADATr324UddO8Lps9tSmFc0q/uGzI= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 6CA836115D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org Cc: Christopher Covington Subject: [PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros Date: Thu, 29 Dec 2016 17:43:33 -0500 Message-Id: <20161229224335.13531-3-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161229224335.13531-1-cov@codeaurora.org> References: <20161229224335.13531-1-cov@codeaurora.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This refactoring will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after preprocessor output of arch/arm64/mm/mmu.c and vmlinux objdump show no functional changes. Signed-off-by: Christopher Covington --- arch/arm64/include/asm/tlbflush.h | 104 +++++++++++++++++++++++++------------- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f28813c 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -25,22 +25,69 @@ #include /* - * Raw TLBI operations. + * Raw TLBI, DSB operations * - * Where necessary, use the __tlbi() macro to avoid asm() - * boilerplate. Drivers and most kernel code should use the TLB - * management routines in preference to the macro below. + * Where necessary, use __tlbi_*dsb() macros to avoid asm() boilerplate. + * Drivers and most kernel code should use the TLB management routines in + * preference to the macros below. * - * The macro can be used as __tlbi(op) or __tlbi(op, arg), depending - * on whether a particular TLBI operation takes an argument or - * not. The macros handles invoking the asm with or without the - * register argument as appropriate. + * The __tlbi_dsb() macro handles invoking the asm without any register + * argument, with a single register argument, and with start (included) + * and end (excluded) range of register arguments. For example: + * + * __tlbi_dsb(op, attr) + * + * tlbi op + * dsb attr + * + * __tlbi_dsb(op, attr, addr) + * + * mov %[addr], =addr + * tlbi op, %[addr] + * dsb attr + * + * __tlbi_range_dsb(op, attr, start, end) + * + * mov %[arg], =start + * mov %[end], =end + * for: + * tlbi op, %[addr] + * add %[addr], %[addr], #(1 << (PAGE_SHIFT - 12)) + * cmp %[addr], %[end] + * b.ne for + * dsb attr */ -#define __TLBI_0(op, arg) asm ("tlbi " #op) -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg)) -#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) -#define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0) +#define __TLBI_FOR_0(ig0, ig1, ig2) +#define __TLBI_INSTR_0(op, ig1, ig2) "tlbi " #op +#define __TLBI_IO_0(ig0, ig1, ig2) : : + +#define __TLBI_FOR_1(ig0, ig1, ig2) +#define __TLBI_INSTR_1(op, ig0, ig1) "tlbi " #op ", %0" +#define __TLBI_IO_1(ig0, arg, ig1) : : "r" (arg) + +#define __TLBI_FOR_2(ig0, start, ig1) unsigned long addr; \ + for (addr = start; addr < end; \ + addr += 1 << (PAGE_SHIFT - 12)) +#define __TLBI_INSTR_2(op, ig0, ig1) "tlbi " #op ", %0" +#define __TLBI_IO_2(ig0, ig1, ig2) : : "r" (addr) + +#define __TLBI_FOR_N(op, a1, a2, n, ...) __TLBI_FOR_##n(op, a1, a2) +#define __TLBI_INSTR_N(op, a1, a2, n, ...) __TLBI_INSTR_##n(op, a1, a2) +#define __TLBI_IO_N(op, a1, a2, n, ...) __TLBI_IO_##n(op, a1, a2) + +#define __TLBI_FOR(op, ...) __TLBI_FOR_N(op, ##__VA_ARGS__, 2, 1, 0) +#define __TLBI_INSTR(op, ...) __TLBI_INSTR_N(op, ##__VA_ARGS__, 2, 1, 0) +#define __TLBI_IO(op, ...) __TLBI_IO_N(op, ##__VA_ARGS__, 2, 1, 0) + +#define __tlbi_asm_dsb(as, op, attr, ...) do { \ + __TLBI_FOR(op, ##__VA_ARGS__) \ + asm (__TLBI_INSTR(op, ##__VA_ARGS__) \ + __TLBI_IO(op, ##__VA_ARGS__)); \ + asm volatile ( as "\ndsb " #attr "\n" \ + : : : "memory"); } while (0) + +#define __tlbi_dsb(...) __tlbi_asm_dsb("", ##__VA_ARGS__) /* * TLB Management @@ -84,16 +131,14 @@ static inline void local_flush_tlb_all(void) { dsb(nshst); - __tlbi(vmalle1); - dsb(nsh); + __tlbi_dsb(vmalle1, nsh); isb(); } static inline void flush_tlb_all(void) { dsb(ishst); - __tlbi(vmalle1is); - dsb(ish); + __tlbi_dsb(vmalle1is, ish); isb(); } @@ -102,8 +147,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) unsigned long asid = ASID(mm) << 48; dsb(ishst); - __tlbi(aside1is, asid); - dsb(ish); + __tlbi_dsb(aside1is, ish, asid); } static inline void flush_tlb_page(struct vm_area_struct *vma, @@ -112,8 +156,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); dsb(ishst); - __tlbi(vale1is, addr); - dsb(ish); + __tlbi_dsb(vale1is, ish, addr); } /* @@ -127,7 +170,6 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, bool last_level) { unsigned long asid = ASID(vma->vm_mm) << 48; - unsigned long addr; if ((end - start) > MAX_TLB_RANGE) { flush_tlb_mm(vma->vm_mm); @@ -138,13 +180,10 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, end = asid | (end >> 12); dsb(ishst); - for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (last_level) - __tlbi(vale1is, addr); - else - __tlbi(vae1is, addr); - } - dsb(ish); + if (last_level) + __tlbi_dsb(vale1is, ish, start, end); + else + __tlbi_dsb(vae1is, ish, start, end); } static inline void flush_tlb_range(struct vm_area_struct *vma, @@ -155,8 +194,6 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - unsigned long addr; - if ((end - start) > MAX_TLB_RANGE) { flush_tlb_all(); return; @@ -166,9 +203,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end end >>= 12; dsb(ishst); - for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) - __tlbi(vaae1is, addr); - dsb(ish); + __tlbi_dsb(vaae1is, ish, start, end); isb(); } @@ -181,8 +216,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, { unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); - __tlbi(vae1is, addr); - dsb(ish); + __tlbi_dsb(vae1is, ish, addr); } #endif