From patchwork Wed Jan 11 14:41:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9510193 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 81B866075C for ; Wed, 11 Jan 2017 14:42:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 772BE28119 for ; Wed, 11 Jan 2017 14:42:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6BBE928577; Wed, 11 Jan 2017 14:42:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1D6C28119 for ; Wed, 11 Jan 2017 14:42:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967438AbdAKOlt (ORCPT ); Wed, 11 Jan 2017 09:41:49 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:40082 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967388AbdAKOlr (ORCPT ); Wed, 11 Jan 2017 09:41:47 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 390A56159A; Wed, 11 Jan 2017 14:41:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1484145706; bh=jiuikHu25NpTGbbJyva9XKuV6vlFN/96EdcBcO8xfYs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VvBQEAC9wJqfwQrqpcucLKc4LCeOtdQC8cIwrgKXlcBYrulcnWM9lcJw4i7J7rFjI TfcaajpNHOOsQNbR53Ozg5q9y2xMpCIJQD5v9u9b/3aQVdt6ivXQjrn6Q8zV5XeRg8 /nyIFU7txdUQACcwJ+GxD11hB4QtW2/Gh7IaUIIU= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 04E5460234; Wed, 11 Jan 2017 14:41:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1484145704; bh=jiuikHu25NpTGbbJyva9XKuV6vlFN/96EdcBcO8xfYs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FP5c2skafmSr9vlyhMAO7YQTFS2LKWw30hgiAzuJy1kIyARmxt+fujJ/mZ/hYNeNE ZDt2V+M/5elKPny3DXRH/3eTx7oy/1OgGK3QcyW+l4en5GZ5YvEnW9Kg3eNeBzWAwr W8GPQxlQ4abMz5xoRUV0pljduWkbkj3z9ew4H4uo= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 04E5460234 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org, Jonathan Corbet , linux-doc@vger.kernel.org Cc: Mark Langsdorf , Mark Salter , Jon Masters , Christopher Covington Subject: [PATCH v3 5/5] arm64: Work around Falkor erratum 1009 Date: Wed, 11 Jan 2017 09:41:18 -0500 Message-Id: <20170111144118.17062-5-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170111144118.17062-1-cov@codeaurora.org> References: <20170111144118.17062-1-cov@codeaurora.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/tlbflush.h | 5 ++++- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 5 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 7151aed..98bef2a 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -64,3 +64,4 @@ stable kernels. | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +| Qualcomm | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 2a80ac9..d13e903 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -490,6 +490,16 @@ config QCOM_FALKOR_ERRATUM_1003 If unsure, say Y. +config QCOM_FALKOR_ERRATUM_1009 + bool "Falkor E1009: Prematurely complete a DSB after a TLBI" + default y + help + Falkor CPU may prematurely complete a DSB following a TLBI xxIS + invalidate maintenance operations. Repeat the TLBI operation one + more time to fix the issue. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 5aaf7ee..55bcd02 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -36,7 +36,8 @@ #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 #define ARM64_HAS_NO_FPSIMD 16 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 17 +#define ARM64_WORKAROUND_REPEAT_TLBI 18 -#define ARM64_NCAPS 18 +#define ARM64_NCAPS 19 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index f28813c..7313cd3 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -85,7 +85,10 @@ asm (__TLBI_INSTR(op, ##__VA_ARGS__) \ __TLBI_IO(op, ##__VA_ARGS__)); \ asm volatile ( as "\ndsb " #attr "\n" \ - : : : "memory"); } while (0) + ALTERNATIVE("nop" "\nnop" "\n", \ + __TLBI_INSTR(op, ##__VA_ARGS__) "\ndsb " #attr "\n", \ + ARM64_WORKAROUND_REPEAT_TLBI) \ + __TLBI_IO(op, ##__VA_ARGS__) : "memory"); } while (0) #define __tlbi_dsb(...) __tlbi_asm_dsb("", ##__VA_ARGS__) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 787b542..e644364 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -137,6 +137,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), }, #endif +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 + { + .desc = "Qualcomm Falkor erratum 1009", + .capability = ARM64_WORKAROUND_REPEAT_TLBI, + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), + }, +#endif { } };