From patchwork Wed Apr 5 06:41:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 9663031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB31260353 for ; Wed, 5 Apr 2017 06:41:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB299284CC for ; Wed, 5 Apr 2017 06:41:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CEEAF28505; Wed, 5 Apr 2017 06:41:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA8D9284CC for ; Wed, 5 Apr 2017 06:41:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754318AbdDEGle (ORCPT ); Wed, 5 Apr 2017 02:41:34 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34309 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753980AbdDEGld (ORCPT ); Wed, 5 Apr 2017 02:41:33 -0400 Received: by mail-pf0-f195.google.com with SMTP id o126so719764pfb.1; Tue, 04 Apr 2017 23:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:in-reply-to:references :organization:mime-version:content-transfer-encoding; bh=1dS6VVRdaYyjkv2PztfRxF9HH1bS+XxmCF2Wyi8UFwc=; b=FXMcJh8nSb6lZXhjKGZvXJ3AEZlRB5WXcHqMJhhw9dX7m3miuhE8c1cRNzcrHow0kz npwkOJMscdo1nKF7hepO0d8zd+dNzEt3aKpBsO020jTzaW6eBTm2our4U9wlYetTKLMP QQ45wvKELln4LZJC8XM8ohwPrNDRoWGcWW5gWh/XPh9JuwMnoGl/0b4DyqAA7PAjnQgu LOeOuEJm9UhBXgwJl//+Mi4z/CNqoLPfV6K+NG1zIptUnWAgRPhuB8h1fVCWlu400R5H xXnXrJeXmgsivaCNprGC9t8AhZxTm2EGY0rJQozCHt325OeqOwVNE9i9Tkx798aqcggi LQRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:organization:mime-version:content-transfer-encoding; bh=1dS6VVRdaYyjkv2PztfRxF9HH1bS+XxmCF2Wyi8UFwc=; b=ZXG+7YU2NBNAllSP8oO3vSKAJ+9qpXb1R2gkl6UxoCYKytiueUAXltZQDaaPZSGyiF pZid0mBAYG2vq9x67j+TAUIsO2Av2mOSLVMKOS3VaqfcCvZxyn4pXCu7vvPTs7E50cM+ rcj9An45aSoBEstj+bguCAfI0bsjSN9eaie3Oks6MHOm6Yc8zXCvi1LtAZMSnBpIpDE3 zOxk7lMdTJ8whDOiJESY+97vvZQrTGj4R2RZvZPO0d6XlZMDmQA/QGNKRbeSHlg0hrUX 5jvf1O/gSUc82DRFksVF96z0PmRcJCx5C7dn2KaoKBU2+hzff+fX4WaMIhzpLZxcwvw9 1C1g== X-Gm-Message-State: AFeK/H34WvZ7EcvTzSnc/YWT7j0hhGl7HywUZ79FvdiZvoR7ot0JrwIT4jv4rN63ZU6u6g== X-Received: by 10.84.176.100 with SMTP id u91mr34586390plb.112.1491374492696; Tue, 04 Apr 2017 23:41:32 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([203.221.48.234]) by smtp.gmail.com with ESMTPSA id r66sm35191737pfi.49.2017.04.04.23.41.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Apr 2017 23:41:31 -0700 (PDT) Date: Wed, 5 Apr 2017 16:41:18 +1000 From: Nicholas Piggin To: Paul Mackerras Cc: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org Subject: Re: [PATCH] KVM: PPC: Book3S HV: Add workaround for msgsync erratum on POWER9 DD1 Message-ID: <20170405164118.7c78fcf5@roar.ozlabs.ibm.com> In-Reply-To: <20170405062611.GB26143@fergus.ozlabs.ibm.com> References: <20170405062611.GB26143@fergus.ozlabs.ibm.com> Organization: IBM X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Wed, 5 Apr 2017 16:26:11 +1000 Paul Mackerras wrote: > On POWER9 DD1 the msgsync instruction doesn't work correctly, but the > new 'darn' (deliver a random number) instruction happens to do an > equivalent function as a side effect. > > Signed-off-by: Paul Mackerras Seems okay to me. I had this, btw (after your feedback) which I'll try to merge for using msgsync in Linux. What do you think? diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h index ddf54f5bbdd1..6b8b28d22323 100644 --- a/arch/powerpc/include/asm/feature-fixups.h +++ b/arch/powerpc/include/asm/feature-fixups.h @@ -66,7 +66,14 @@ label##5: \ #define END_FTR_SECTION(msk, val) \ END_FTR_SECTION_NESTED(msk, val, 97) +#define END_FTR_SECTION_NESTED_IFSET(msk, label) \ + END_FTR_SECTION_NESTED((msk), (msk), label) + #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) + +#define END_FTR_SECTION_NESTED_IFCLR(msk, label) \ + END_FTR_SECTION_NESTED((msk), 0, label) + #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) /* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */ diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index e7d6d86563ee..44009dfeab69 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -134,6 +134,7 @@ #define PPC_INST_COPY 0x7c00060c #define PPC_INST_COPY_FIRST 0x7c20060c #define PPC_INST_CP_ABORT 0x7c00068c +#define PPC_INST_DARN 0x7c0005e6 #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec @@ -161,6 +162,7 @@ #define PPC_INST_MFTMR 0x7c0002dc #define PPC_INST_MSGSND 0x7c00019c #define PPC_INST_MSGCLR 0x7c0001dc +#define PPC_INST_MSGSYNC 0x7c0006ec #define PPC_INST_MSGSNDP 0x7c00011c #define PPC_INST_MTTMR 0x7c0003dc #define PPC_INST_NOP 0x60000000 @@ -310,6 +312,7 @@ #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) #define __PPC_XT(s) __PPC_XS(s) #define __PPC_T_TLB(t) (((t) & 0x3) << 21) +#define __PPC_L_DARN(l) (((l) & 0x3) << 16) #define __PPC_WC(w) (((w) & 0x3) << 21) #define __PPC_WS(w) (((w) & 0x1f) << 11) #define __PPC_SH(s) __PPC_WS(s) @@ -333,6 +336,8 @@ /* Deal with instructions that older assemblers aren't aware of */ #define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT) +#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ + ___PPC_RT(t) | __PPC_L_DARN(l)) #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ __PPC_RA(a) | __PPC_RB(b)) #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ @@ -345,6 +350,7 @@ ___PPC_RB(b) | __PPC_EH(eh)) #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ ___PPC_RB(b)) +#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC) #define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ ___PPC_RB(b)) #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 359c44341761..00576c10fe6c 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -402,6 +402,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) FTR_SECTION_ELSE_NESTED(848); \ mtocrf (FXM), RS; \ ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) + +#define MSGSYNC(reg) \ + BEGIN_FTR_SECTION_NESTED(849); \ + \ + BEGIN_FTR_SECTION_NESTED(850); \ + PPC_MSGSYNC; \ + lwsync; \ + FTR_SECTION_ELSE_NESTED(850); \ + PPC_DARN(reg, 2); \ + lwsync; \ + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POWER9_DD1, 850); \ + \ + END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE|CPU_FTR_ARCH_300, 849) #endif /* diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 7c6477d1840a..f8cf7b6a2aaa 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1239,6 +1239,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) /* Hypervisor doorbell - exit only if host IPI flag set */ cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL bne 3f + MSGSYNC(0) lbz r0, HSTATE_HOST_IPI(r13) cmpwi r0, 0 beq 4f