From patchwork Tue May 9 08:56:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 9717319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BAFFA60365 for ; Tue, 9 May 2017 08:56:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0B5528389 for ; Tue, 9 May 2017 08:56:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5936283CA; Tue, 9 May 2017 08:56:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FC3B28389 for ; Tue, 9 May 2017 08:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751994AbdEII4b (ORCPT ); Tue, 9 May 2017 04:56:31 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:36828 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751140AbdEII41 (ORCPT ); Tue, 9 May 2017 04:56:27 -0400 Received: by mail-wm0-f51.google.com with SMTP id u65so3301861wmu.1 for ; Tue, 09 May 2017 01:56:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ke8XdbRFfkrlDSyyh93j1GUH6hl1bixL1rR7NdZlzo8=; b=eqjUwCchNn4yFLJgC1M1RpQhiaAmFTsWWDoNZIe0V4rg07JHjO8In8zAgmQC7mdrRw sx+b7/KTN0PghEUFr2BR2lCTres1onY971Ky3xsJ/TUJ2VvL0tQVcNRaDKgZ6K9d39re lN5YONowwP2Idb07RilS5/SrZrWoFEYMG+ky8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ke8XdbRFfkrlDSyyh93j1GUH6hl1bixL1rR7NdZlzo8=; b=uP+SHD9HG5qPEU/g8IgutQFB7rODTleDcd5GEUp+9YOXXq+4jgacYr1TJytSMh0INT /4u1Fjg+2CyoiBV+36XYRNyKLiOJAifacHczRhKsvmuthMJIoNUhETNp9MHRMgPkEaM4 ZYIcs5t4yXrNyGsaRhX6w5XZ8Qkq3aWqrHUQgpD2+MJkmYJ8bsJVFd09hG6OhkpD1cmh UopJzG353BtnVvbYu9BwLz9UAx/Te1AbW3fXWElYK0lWFH3LwohZleqmUSD6yWhF1DPw Ru6oZWDM82aY/ZpNZWQQdAktjf0i3lyb8wsOLJ7NhC3TA1pvZFLGukuPBfuSwKiWXK2l 1LLA== X-Gm-Message-State: AN3rC/5IbDs4Em03R3r5PS/sFCTy9j5cNDY3Yvkb9cmwBErNAJUPGxT3 6fPTjEvaVVMFS54K X-Received: by 10.80.149.81 with SMTP id v17mr46188834eda.76.1494320185895; Tue, 09 May 2017 01:56:25 -0700 (PDT) Received: from localhost.localdomain (xd93ddc2d.cust.hiper.dk. [217.61.220.45]) by smtp.gmail.com with ESMTPSA id f40sm8376265edb.7.2017.05.09.01.56.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 May 2017 01:56:25 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Cc: kvm@vger.kernel.org, Marc Zyngier , Eric Auger , Christoffer Dall Subject: [PATCH v2 01/11] KVM: arm/arm64: Clarification and relaxation to ITS save/restore ABI Date: Tue, 9 May 2017 10:56:08 +0200 Message-Id: <20170509085618.28311-2-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170509085618.28311-1-cdall@linaro.org> References: <20170509085618.28311-1-cdall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Clarify what is meant by the save/restore ABI only supporting virtual physical interrupts. Relax the requirement of the order that the collection entries are written in and be clear that there is no particular ordering enforced. Some cosmetic changes in the capitalization of ID names to align with the GICv3 manual and remove the empty line in the bottom of the patch. Signed-off-by: Christoffer Dall Reviewed-by: Eric Auger --- Documentation/virtual/kvm/devices/arm-vgic-its.txt | 23 +++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/virtual/kvm/devices/arm-vgic-its.txt b/Documentation/virtual/kvm/devices/arm-vgic-its.txt index ba132e9..eb06beb 100644 --- a/Documentation/virtual/kvm/devices/arm-vgic-its.txt +++ b/Documentation/virtual/kvm/devices/arm-vgic-its.txt @@ -97,8 +97,8 @@ Groups: The following ordering must be followed when restoring the GIC and the ITS: a) restore all guest memory and create vcpus b) restore all redistributors -c) initialize the ITS and then provide its base address - (KVM_DEV_ARM_VGIC_CTRL_INIT, KVM_DEV_ARM_VGIC_GRP_ADDR) +c) provide the its base address + (KVM_DEV_ARM_VGIC_GRP_ADDR) d) restore the ITS in the following order: 1. Restore GITS_CBASER 2. Restore all other GITS_ registers, except GITS_CTLR! @@ -110,12 +110,14 @@ Then vcpus can be started. ITS Table ABI REV0: ------------------- - Revision 0 of the ABI only supports physical LPIs. + Revision 0 of the ABI only supports the features of a virtual GICv3, and does + not support a virtual GICv4 with support for direct injection of virtual + interrupts for nested hypervisors. - The device table and ITT are indexed by the deviceid and eventid, - respectively. The collection table is not indexed by collectionid: - CTEs are written in the table in the order of collection creation. All - entries are 8 bytes. + The device table and ITT are indexed by the DeviceID and EventID, + respectively. The collection table is not indexed by CollectionID, and the + entries in the collection are listed in no particular order. + All entries are 8 bytes. Device Table Entry (DTE): @@ -126,10 +128,10 @@ Then vcpus can be started. - V indicates whether the entry is valid. If not, other fields are not meaningful. - next: equals to 0 if this entry is the last one; otherwise it - corresponds to the deviceid offset to the next DTE, capped by + corresponds to the DeviceID offset to the next DTE, capped by 2^14 -1. - ITT_addr matches bits [51:8] of the ITT address (256 Byte aligned). - - Size specifies the supported number of bits for the eventid, + - Size specifies the supported number of bits for the EventID, minus one Collection Table Entry (CTE): @@ -151,8 +153,7 @@ Then vcpus can be started. where: - next: equals to 0 if this entry is the last one; otherwise it corresponds - to the eventid offset to the next ITE capped by 2^16 -1. + to the EventID offset to the next ITE capped by 2^16 -1. - pINTID is the physical LPI ID; if zero, it means the entry is not valid and other fields are not meaningful. - ICID is the collection ID -