From patchwork Wed Oct 18 11:34:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 10014385 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2736B60211 for ; Wed, 18 Oct 2017 11:34:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C17428B24 for ; Wed, 18 Oct 2017 11:34:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 108B228B27; Wed, 18 Oct 2017 11:34:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 19F3028B24 for ; Wed, 18 Oct 2017 11:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754074AbdJRLeG (ORCPT ); Wed, 18 Oct 2017 07:34:06 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:56263 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753119AbdJRLeE (ORCPT ); Wed, 18 Oct 2017 07:34:04 -0400 Received: by mail-wm0-f65.google.com with SMTP id u138so9666804wmu.4 for ; Wed, 18 Oct 2017 04:34:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8YJF3qHBXGoaBSf3Pqu+sxj5omeoB5wchVMcAPG60Nc=; b=UmvGQr0j5J319P7S2MI8sTuKKn7eZDFCyNzVIPaEHcDQB0sdXQrzzGHAAQuI7Pe0Zl h8DTv7/c/Lv9r7pWcrtdJJ4dBRZwb1vU2+HJptu86Fj6MaC+LvGdlVgZh+0dWrDdGxNv vaN6mj8pL56dyEUi+3p9c5NCSbvyxLHo+kog4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8YJF3qHBXGoaBSf3Pqu+sxj5omeoB5wchVMcAPG60Nc=; b=IQfAvZzZfPNTsw5PqRbI1u9n8SVKYdW+y2fBiS4XNt+nTD6OM5pPjEnBdrPlkffbmu KFEWT9JX+wKtm9PsKRBfz/XOdOJ2tf9unZ4JV6BHz+yEzTO5AzwAvFeDp4oQ7KiaX/O2 c5dABkq3ki14wMsbD9AZxvRM46Krqx9b8tCzn+aBUDO+lQBJGmNQXoSu0NCyj+k9VBqK pfBZrh5ItkosDSIR7mvbT+cnHQamUV2FRHgu1fhSxQwbrMdpqG6vJVePDKM+f9UVCEKf 8qs2HQBgJZd7Ukrj7qAIe5eIZ1jsGEwoOkuM7Pbo1w5mn9/gOYbfrTu5K/0uDLbsaP3f jOjg== X-Gm-Message-State: AMCzsaUPO1yfkP4xjHylG9g0joo2z9nzYeKMC9s/CNqwO6YHPSowfuR9 +VnFnpRwTbZVNhsjUPlYZPJTkg== X-Google-Smtp-Source: ABhQp+Ro9Ub/UrMwVj1cJKlIy//26kfcFHRHqshz6vzbzhEK7v0aspeRtNh2BdO2EJa/rrUyD3TI5A== X-Received: by 10.80.158.4 with SMTP id z4mr7267631ede.183.1508326443304; Wed, 18 Oct 2017 04:34:03 -0700 (PDT) Received: from localhost (xd93dd96b.cust.hiper.dk. [217.61.217.107]) by smtp.gmail.com with ESMTPSA id y40sm8536139ede.0.2017.10.18.04.34.01 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:34:02 -0700 (PDT) Date: Wed, 18 Oct 2017 13:34:05 +0200 From: Christoffer Dall To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Will Deacon , Catalin Marinas , Mark Rutland Subject: Re: [PATCH v3 03/20] arm64: Use the physical counter when available for read_cycles Message-ID: <20171018113405.GA8900@cbox> References: <20170923004207.22356-1-cdall@linaro.org> <20170923004207.22356-4-cdall@linaro.org> <9b06425f-7c2c-d44a-cd6c-aeaa4b76849c@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <9b06425f-7c2c-d44a-cd6c-aeaa4b76849c@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, Oct 09, 2017 at 05:21:24PM +0100, Marc Zyngier wrote: > On 23/09/17 01:41, Christoffer Dall wrote: > > Currently get_cycles() is hardwired to arch_counter_get_cntvct() on > > arm64, but as we move to using the physical timer for the in-kernel > > time-keeping, we need to make that more flexible. > > > > First, we need to make sure the physical counter can be read on equal > > terms to the virtual counter, which includes adding physical counter > > read functions for timers that require errata. > > > > Second, we need to make a choice between reading the physical vs virtual > > counter, depending on which timer is used for time keeping in the kernel > > otherwise. We can do this using a static key to avoid a performance > > penalty during runtime when reading the counter. > > > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Mark Rutland > > Cc: Marc Zyngier > > Signed-off-by: Christoffer Dall > > Right. I should have read patch #3. I'm an idiot. > > > --- > > arch/arm64/include/asm/arch_timer.h | 15 ++++++++++++--- > > arch/arm64/include/asm/timex.h | 2 +- > > drivers/clocksource/arm_arch_timer.c | 32 ++++++++++++++++++++++++++++++-- > > 3 files changed, 43 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h > > index 1859a1c..c56d8cd 100644 > > --- a/arch/arm64/include/asm/arch_timer.h > > +++ b/arch/arm64/include/asm/arch_timer.h > > @@ -30,6 +30,8 @@ > > > > #include > > > > +extern struct static_key_false arch_timer_phys_counter_available; > > + > > #if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND) > > extern struct static_key_false arch_timer_read_ool_enabled; > > #define needs_unstable_timer_counter_workaround() \ > > @@ -52,6 +54,7 @@ struct arch_timer_erratum_workaround { > > const char *desc; > > u32 (*read_cntp_tval_el0)(void); > > u32 (*read_cntv_tval_el0)(void); > > + u64 (*read_cntpct_el0)(void); > > u64 (*read_cntvct_el0)(void); > > int (*set_next_event_phys)(unsigned long, struct clock_event_device *); > > int (*set_next_event_virt)(unsigned long, struct clock_event_device *); > > @@ -148,10 +151,8 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) > > > > static inline u64 arch_counter_get_cntpct(void) > > { > > - u64 cval; > > isb(); > > - asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); > > - return cval; > > + return arch_timer_reg_read_stable(cntpct_el0); > > } > > > > static inline u64 arch_counter_get_cntvct(void) > > @@ -160,6 +161,14 @@ static inline u64 arch_counter_get_cntvct(void) > > return arch_timer_reg_read_stable(cntvct_el0); > > } > > > > +static inline u64 arch_counter_get_cycles(void) > > +{ > > + if (static_branch_unlikely(&arch_timer_phys_counter_available)) > > + return arch_counter_get_cntpct(); > > + else > > + return arch_counter_get_cntvct(); > > +} > > + > > static inline int arch_timer_arch_init(void) > > { > > return 0; > > diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h > > index 81a076e..c0d214c 100644 > > --- a/arch/arm64/include/asm/timex.h > > +++ b/arch/arm64/include/asm/timex.h > > @@ -22,7 +22,7 @@ > > * Use the current timer as a cycle counter since this is what we use for > > * the delay loop. > > */ > > -#define get_cycles() arch_counter_get_cntvct() > > +#define get_cycles() arch_counter_get_cycles() > > Why can't this be arch_timer_read_counter() instead? Is there any > measurable advantage in using a static key compared to a memory > indirection? > No reason. I think I thought there was an include dependency issue that led me to do it the other way, but I must have confused myself, because using arch_timer_read_counter seems to work perfectly well. > > > > #include > > > > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > > index 9b3322a..f35da20 100644 > > --- a/drivers/clocksource/arm_arch_timer.c > > +++ b/drivers/clocksource/arm_arch_timer.c > > @@ -77,6 +77,9 @@ static bool arch_timer_mem_use_virtual; > > static bool arch_counter_suspend_stop; > > static bool vdso_default = true; > > > > +DEFINE_STATIC_KEY_FALSE(arch_timer_phys_counter_available); > > +EXPORT_SYMBOL_GPL(arch_timer_phys_counter_available); > > + > > static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); > > > > static int __init early_evtstrm_cfg(char *buf) > > @@ -217,6 +220,11 @@ static u32 notrace fsl_a008585_read_cntv_tval_el0(void) > > return __fsl_a008585_read_reg(cntv_tval_el0); > > } > > > > +static u64 notrace fsl_a008585_read_cntpct_el0(void) > > +{ > > + return __fsl_a008585_read_reg(cntpct_el0); > > +} > > + > > static u64 notrace fsl_a008585_read_cntvct_el0(void) > > { > > return __fsl_a008585_read_reg(cntvct_el0); > > @@ -258,6 +266,11 @@ static u32 notrace hisi_161010101_read_cntv_tval_el0(void) > > return __hisi_161010101_read_reg(cntv_tval_el0); > > } > > > > +static u64 notrace hisi_161010101_read_cntpct_el0(void) > > +{ > > + return __hisi_161010101_read_reg(cntpct_el0); > > +} > > + > > static u64 notrace hisi_161010101_read_cntvct_el0(void) > > { > > return __hisi_161010101_read_reg(cntvct_el0); > > @@ -288,6 +301,15 @@ static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { > > #endif > > > > #ifdef CONFIG_ARM64_ERRATUM_858921 > > +static u64 notrace arm64_858921_read_cntpct_el0(void) > > +{ > > + u64 old, new; > > + > > + old = read_sysreg(cntpct_el0); > > + new = read_sysreg(cntpct_el0); > > + return (((old ^ new) >> 32) & 1) ? old : new; > > +} > > + > > static u64 notrace arm64_858921_read_cntvct_el0(void) > > { > > u64 old, new; > > @@ -346,6 +368,7 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { > > .desc = "Freescale erratum a005858", > > .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, > > .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, > > + .read_cntpct_el0 = fsl_a008585_read_cntpct_el0, > > .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, > > .set_next_event_phys = erratum_set_next_event_tval_phys, > > .set_next_event_virt = erratum_set_next_event_tval_virt, > > @@ -358,6 +381,7 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { > > .desc = "HiSilicon erratum 161010101", > > .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, > > .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, > > + .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, > > .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, > > .set_next_event_phys = erratum_set_next_event_tval_phys, > > .set_next_event_virt = erratum_set_next_event_tval_virt, > > @@ -368,6 +392,7 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { > > .desc = "HiSilicon erratum 161010101", > > .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, > > .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, > > + .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, > > .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, > > .set_next_event_phys = erratum_set_next_event_tval_phys, > > .set_next_event_virt = erratum_set_next_event_tval_virt, > > @@ -378,6 +403,7 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { > > .match_type = ate_match_local_cap_id, > > .id = (void *)ARM64_WORKAROUND_858921, > > .desc = "ARM erratum 858921", > > + .read_cntpct_el0 = arm64_858921_read_cntpct_el0, > > .read_cntvct_el0 = arm64_858921_read_cntvct_el0, > > }, > > #endif > > @@ -890,10 +916,12 @@ static void __init arch_counter_register(unsigned type) > > > > /* Register the CP15 based counter if we have one */ > > if (type & ARCH_TIMER_TYPE_CP15) { > > - if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) > > + if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) { > > arch_timer_read_counter = arch_counter_get_cntvct; > > - else > > + } else { > > arch_timer_read_counter = arch_counter_get_cntpct; > > + static_branch_enable(&arch_timer_phys_counter_available); > > + } > > > > clocksource_counter.archdata.vdso_direct = vdso_default; > > } else { > > > > In my reply to patch #2, I had the following hunk: > > @@ -310,7 +329,7 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long > struct clock_event_device *clk) > { > unsigned long ctrl; > - u64 cval = evt + arch_counter_get_cntvct(); > + u64 cval = evt + arch_timer_read_counter(); > > ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); > ctrl |= ARCH_TIMER_CTRL_ENABLE; > > Once we start using a different timer, this could well have an effect... > Right, but wouldn't the following be a more correct way to go about it then: Thanks, -Christoffer diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9a7b359..07f19db 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -329,16 +329,19 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long struct clock_event_device *clk) { unsigned long ctrl; - u64 cval = evt + arch_timer_read_counter(); + u64 cval; ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; - if (access == ARCH_TIMER_PHYS_ACCESS) + if (access == ARCH_TIMER_PHYS_ACCESS) { + cval = evt + arch_counter_get_cntpct(); write_sysreg(cval, cntp_cval_el0); - else + } else { + cval = evt + arch_counter_get_cntvct(); write_sysreg(cval, cntv_cval_el0); + } arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); }