diff mbox

[5/5] KVM: x86: ioapic: Preserve read-only values in the redirection table

Message ID 20171105135233.34572-6-nikita.leshchenko@oracle.com (mailing list archive)
State New, archived
Headers show

Commit Message

Nikita Leshenko Nov. 5, 2017, 1:52 p.m. UTC
According to 82093AA (IOAPIC) manual, Remote IRR and Delivery Status are
read-only. QEMU implements the bits as RO in commit 479c2a1cb7fb
("ioapic: keep RO bits for IOAPIC entry").

Signed-off-by: Nikita Leshenko <nikita.leshchenko@oracle.com>
Reviewed-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
 arch/x86/kvm/ioapic.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Wanpeng Li Nov. 6, 2017, 3:20 a.m. UTC | #1
2017-11-05 21:52 GMT+08:00 Nikita Leshenko <nikita.leshchenko@oracle.com>:
> According to 82093AA (IOAPIC) manual, Remote IRR and Delivery Status are
> read-only. QEMU implements the bits as RO in commit 479c2a1cb7fb
> ("ioapic: keep RO bits for IOAPIC entry").
>
> Signed-off-by: Nikita Leshenko <nikita.leshchenko@oracle.com>
> Reviewed-by: Liran Alon <liran.alon@oracle.com>
> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>

> ---
>  arch/x86/kvm/ioapic.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
> index 163d340ee5f8..4e822ad363f3 100644
> --- a/arch/x86/kvm/ioapic.c
> +++ b/arch/x86/kvm/ioapic.c
> @@ -276,6 +276,7 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>  {
>         unsigned index;
>         bool mask_before, mask_after;
> +       int old_remote_irr, old_delivery_status;
>         union kvm_ioapic_redirect_entry *e;
>
>         switch (ioapic->ioregsel) {
> @@ -298,6 +299,9 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>                         return;
>                 e = &ioapic->redirtbl[index];
>                 mask_before = e->fields.mask;
> +               /* Preserve read-only fields */
> +               old_remote_irr = e->fields.remote_irr;
> +               old_delivery_status = e->fields.delivery_status;
>                 if (ioapic->ioregsel & 1) {
>                         e->bits &= 0xffffffff;
>                         e->bits |= (u64) val << 32;
> @@ -305,6 +309,8 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>                         e->bits &= ~0xffffffffULL;
>                         e->bits |= (u32) val;
>                 }
> +               e->fields.remote_irr = old_remote_irr;
> +               e->fields.delivery_status = old_delivery_status;
>
>                 /*
>                  * Some OSes (Linux, Xen) assume that Remote IRR bit will
> --
> 2.13.3
>
Steve Rutherford Nov. 8, 2017, 12:18 a.m. UTC | #2
Reviewed-by: Steve Rutherford <srutherford@google.com>

On Sun, Nov 5, 2017 at 7:20 PM, Wanpeng Li <kernellwp@gmail.com> wrote:
> 2017-11-05 21:52 GMT+08:00 Nikita Leshenko <nikita.leshchenko@oracle.com>:
>> According to 82093AA (IOAPIC) manual, Remote IRR and Delivery Status are
>> read-only. QEMU implements the bits as RO in commit 479c2a1cb7fb
>> ("ioapic: keep RO bits for IOAPIC entry").
>>
>> Signed-off-by: Nikita Leshenko <nikita.leshchenko@oracle.com>
>> Reviewed-by: Liran Alon <liran.alon@oracle.com>
>> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
>
> Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
>
>> ---
>>  arch/x86/kvm/ioapic.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
>> index 163d340ee5f8..4e822ad363f3 100644
>> --- a/arch/x86/kvm/ioapic.c
>> +++ b/arch/x86/kvm/ioapic.c
>> @@ -276,6 +276,7 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>>  {
>>         unsigned index;
>>         bool mask_before, mask_after;
>> +       int old_remote_irr, old_delivery_status;
>>         union kvm_ioapic_redirect_entry *e;
>>
>>         switch (ioapic->ioregsel) {
>> @@ -298,6 +299,9 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>>                         return;
>>                 e = &ioapic->redirtbl[index];
>>                 mask_before = e->fields.mask;
>> +               /* Preserve read-only fields */
>> +               old_remote_irr = e->fields.remote_irr;
>> +               old_delivery_status = e->fields.delivery_status;
>>                 if (ioapic->ioregsel & 1) {
>>                         e->bits &= 0xffffffff;
>>                         e->bits |= (u64) val << 32;
>> @@ -305,6 +309,8 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
>>                         e->bits &= ~0xffffffffULL;
>>                         e->bits |= (u32) val;
>>                 }
>> +               e->fields.remote_irr = old_remote_irr;
>> +               e->fields.delivery_status = old_delivery_status;
>>
>>                 /*
>>                  * Some OSes (Linux, Xen) assume that Remote IRR bit will
>> --
>> 2.13.3
>>
diff mbox

Patch

diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
index 163d340ee5f8..4e822ad363f3 100644
--- a/arch/x86/kvm/ioapic.c
+++ b/arch/x86/kvm/ioapic.c
@@ -276,6 +276,7 @@  static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 {
 	unsigned index;
 	bool mask_before, mask_after;
+	int old_remote_irr, old_delivery_status;
 	union kvm_ioapic_redirect_entry *e;
 
 	switch (ioapic->ioregsel) {
@@ -298,6 +299,9 @@  static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 			return;
 		e = &ioapic->redirtbl[index];
 		mask_before = e->fields.mask;
+		/* Preserve read-only fields */
+		old_remote_irr = e->fields.remote_irr;
+		old_delivery_status = e->fields.delivery_status;
 		if (ioapic->ioregsel & 1) {
 			e->bits &= 0xffffffff;
 			e->bits |= (u64) val << 32;
@@ -305,6 +309,8 @@  static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 			e->bits &= ~0xffffffffULL;
 			e->bits |= (u32) val;
 		}
+		e->fields.remote_irr = old_remote_irr;
+		e->fields.delivery_status = old_delivery_status;
 
 		/*
 		 * Some OSes (Linux, Xen) assume that Remote IRR bit will