From patchwork Tue Mar 6 16:26:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10262269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 71EDD60211 for ; Tue, 6 Mar 2018 16:59:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60604285BA for ; Tue, 6 Mar 2018 16:59:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 54475290B9; Tue, 6 Mar 2018 16:59:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D066F285BA for ; Tue, 6 Mar 2018 16:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753956AbeCFQ7k (ORCPT ); Tue, 6 Mar 2018 11:59:40 -0500 Received: from orth.archaic.org.uk ([81.2.115.148]:49492 "EHLO orth.archaic.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753598AbeCFQ7j (ORCPT ); Tue, 6 Mar 2018 11:59:39 -0500 X-Greylist: delayed 1969 seconds by postgrey-1.27 at vger.kernel.org; Tue, 06 Mar 2018 11:59:39 EST Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etFQN-0004dw-Vn; Tue, 06 Mar 2018 16:26:47 +0000 From: Peter Maydell To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , linux-arm-kernel@lists.infradead.org Subject: [PATCH] KVM: arm: reserve bit in KVM_REG_ARM encoding for secure/nonsecure Date: Tue, 6 Mar 2018 16:26:46 +0000 Message-Id: <20180306162646.7646-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have a KVM_REG_ARM encoding that we use to expose KVM guest registers to userspace. Define that bit 28 in this encoding indicates secure vs nonsecure, so we can distinguish the secure and nonsecure banked versions of a banked AArch32 register. For KVM currently, all guest registers are nonsecure, but defining the bit is useful for userspace. In particular, QEMU uses this encoding as part of its on-the-wire migration format, and needs to be able to describe secure-bank registers when it is migrating (fully emulated) EL3-enabled CPUs. Signed-off-by: Peter Maydell --- arch/arm/include/uapi/asm/kvm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index 6edd177bb1c7..e0d742c36cb1 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -135,6 +135,11 @@ struct kvm_arch_memory_slot { #define KVM_REG_ARM_CRM_SHIFT 7 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 #define KVM_REG_ARM_32_CRN_SHIFT 11 +/* For KVM currently all guest registers are nonsecure, but we reserve a bit + * in the encoding to distinguish secure from nonsecure for banked registers. + */ +#define KVM_REG_ARM_SECURE_MASK 0x0000000010000000 +#define KVM_REG_ARM_SECURE_SHIFT 28 #define ARM_CP15_REG_SHIFT_MASK(x,n) \ (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)