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[v8,2/8] i386: Add cache information in X86CPUDefinition

Message ID 20180510204148.11687-3-babu.moger@amd.com (mailing list archive)
State New, archived
Headers show

Commit Message

Babu Moger May 10, 2018, 8:41 p.m. UTC 
Add cache information in X86CPUDefinition and CPUX86State.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target/i386/cpu.c | 1 +
 target/i386/cpu.h | 7 +++++++
 2 files changed, 8 insertions(+)
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Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 18835400f1..3a74c4b1e4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1105,6 +1105,7 @@  struct X86CPUDefinition {
     int stepping;
     FeatureWordArray features;
     const char *model_id;
+    CPUCaches *cache_info;
 };
 
 static X86CPUDefinition builtin_x86_defs[] = {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index fa03e2ced4..372f8b7ef5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1096,6 +1096,12 @@  typedef struct CPUCacheInfo {
 } CPUCacheInfo;
 
 
+typedef struct CPUCaches {
+        CPUCacheInfo l1d_cache;
+        CPUCacheInfo l1i_cache;
+        CPUCacheInfo l2_cache;
+        CPUCacheInfo l3_cache;
+} CPUCaches;
 
 typedef struct CPUX86State {
     /* standard registers */
@@ -1282,6 +1288,7 @@  typedef struct CPUX86State {
     /* Features that were explicitly enabled/disabled */
     FeatureWordArray user_features;
     uint32_t cpuid_model[12];
+    CPUCaches *cache_info;
 
     /* MTRRs */
     uint64_t mtrr_fixed[11];