@@ -70,8 +70,6 @@ static void tsc_deadline_timer_isr(isr_regs_t *regs)
static void start_tsc_deadline_timer(void)
{
handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
- irq_enable();
-
wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC)+delta);
asm volatile ("nop");
}
@@ -116,10 +114,9 @@ int main(int argc, char **argv)
breakmax = argc <= 3 ? 0 : atol(argv[3]);
printf("breakmax=%d\n", breakmax);
test_tsc_deadline_timer();
- irq_enable();
do {
- asm volatile("hlt");
+ safe_halt();
} while (!hitmax && table_idx < size);
for (i = 0; i < table_idx; i++) {
This patch fixes a tscdeadline_latency hang when specifying a very small breakmax value. It's easily reproduced on my host when set breakmax to e.g. 10 TSC clocks. The problem is test_tsc_deadline_timer() can be very slow because we've got printf() in there. So when reach the main loop we might have already triggered the IRQ handler for multiple times and we might have triggered the hitmax condition which will turn IRQ off. Then with no IRQ that first HLT instruction can last forever. Fix this by don't enable irq and use safe_halt() as suggested by Sean Christopherson. Signed-off-by: Peter Xu <peterx@redhat.com> --- x86/tscdeadline_latency.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)