From patchwork Wed Sep 25 11:19:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11160457 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 552B31709 for ; Wed, 25 Sep 2019 11:20:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2920B21D7C for ; Wed, 25 Sep 2019 11:20:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569410402; bh=9YW6iTW7eUnlQgYZiffS3vbPU35uBV8L6gHK8GJP18o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=V0kp4k0QS9EeNesecqhWaUYQGD6NU6bJODKWSUZz3nIUnKwINqF3tsDAsj5m9mvjF FprYNxbek29B3LUpKpjnQh47Usw3kdKO4UThcLYKZACra2AUSgFPdSMibyuD047gQ/ w7pcDKzPMJMCFdqZvrTLmi4X+iBswjfVlHX0kjKs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391054AbfIYLUB (ORCPT ); Wed, 25 Sep 2019 07:20:01 -0400 Received: from foss.arm.com ([217.140.110.172]:46894 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391027AbfIYLUA (ORCPT ); Wed, 25 Sep 2019 07:20:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB0341570; Wed, 25 Sep 2019 04:19:59 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A436D3F694; Wed, 25 Sep 2019 04:19:58 -0700 (PDT) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Will Deacon , Mark Rutland , Catalin Marinas , James Morse , Suzuki K Poulose , Julien Thierry Subject: [PATCH 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Date: Wed, 25 Sep 2019 12:19:39 +0100 Message-Id: <20190925111941.88103-4-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190925111941.88103-1-maz@kernel.org> References: <20190925111941.88103-1-maz@kernel.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When erratum 1319367 is being worked around, special care must be taken not to allow the page table walker to populate TLBs while we have the stage-2 translation enabled (which would otherwise result in a bizare mix of the host S1 and the guest S2). We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2 configuration, and clear the same bits after having disabled S2. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/tlb.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index eb0efc5557f3..4ef0bf0d76a6 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -63,6 +63,22 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm, static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm, struct tlb_inv_context *cxt) { + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { + u64 val; + + /* + * For CPUs that are affected by ARM 1319367, we need to + * avoid a host Stage-1 walk while we have the guest's + * Stage-2 set in the VTTBR in order to invalidate TLBs. + * We're guaranteed that the S1 MMU is enabled, so we can + * simply set the EPD bits to avoid any further TLB fill. + */ + val = cxt->tcr = read_sysreg_el1(SYS_TCR); + val |= TCR_EPD1_MASK | TCR_EPD0_MASK; + write_sysreg_el1(val, SYS_TCR); + isb(); + } + __load_guest_stage2(kvm); isb(); } @@ -100,6 +116,13 @@ static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm, struct tlb_inv_context *cxt) { write_sysreg(0, vttbr_el2); + + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { + /* Ensure stage-2 is actually disabled */ + isb(); + /* Restore the host's TCR_EL1 */ + write_sysreg_el1(cxt->tcr, SYS_TCR); + } } static void __hyp_text __tlb_switch_to_host(struct kvm *kvm,