From patchwork Fri Dec 20 14:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D85D7109A for ; Fri, 20 Dec 2019 14:34:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B6CAA206CB for ; Fri, 20 Dec 2019 14:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727768AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from foss.arm.com ([217.140.110.172]:51180 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CAC431B; Fri, 20 Dec 2019 06:30:34 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B39603F718; Fri, 20 Dec 2019 06:30:32 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 01/18] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Date: Fri, 20 Dec 2019 14:30:08 +0000 Message-Id: <20191220143025.33853-2-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla It's not entirely clear for the binding document that the only way to express ARM SPE affined to a subset of CPUs on a heterogeneous systems is through the use of PPI partitions available in the interrupt controller bindings. Let's make it clear. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt index 93372f2a7df9..4f4815800f6e 100644 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer. "arm,statistical-profiling-extension-v1" - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. + SPE is only supported on a subset of the CPUs, a PPI partition + described in the arm,gic-v3 binding must be used to describe + the set of CPUs this interrupt is affine to. ** Example: