@@ -269,10 +269,17 @@ static void test_timer(struct timer_info *info)
/* Disable the timer again and prepare to take interrupts */
info->write_ctl(0);
+ info->irq_received = false;
set_timer_irq_enabled(info, true);
+ report(!info->irq_received, "no interrupt when timer is disabled");
report(!timer_pending(info) && gic_timer_state(info) == GIC_STATE_INACTIVE,
"interrupt signal no longer pending");
+ info->write_cval(now - 1);
+ info->write_ctl(ARCH_TIMER_CTL_ENABLE | ARCH_TIMER_CTL_IMASK);
+ report(timer_pending(info) && gic_timer_state(info) == GIC_STATE_INACTIVE,
+ "interrupt signal not pending");
+
report(test_cval_10msec(info), "latency within 10 ms");
report(info->irq_received, "interrupt received");
@@ -132,7 +132,7 @@ groups = psci
[timer]
file = timer.flat
groups = timer
-timeout = 8s
+timeout = 10s
arch = arm64
# Exit tests
When the timer is disabled (the *_CTL_EL0.ENABLE bit is clear) or the timer interrupt is masked at the timer level (the *_CTL_EL0.IMASK bit is set), timer interrupts must not be pending or asserted by the VGIC. However, only when the timer interrupt is masked, we can still check that the timer condition is met by reading the *_CTL_EL0.ISTATUS bit. This test was used to discover a bug and test the fix introduced by KVM commit 16e604a437c8 ("KVM: arm/arm64: vgic: Reevaluate level sensitive interrupts on enable"). Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- arm/timer.c | 7 +++++++ arm/unittests.cfg | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-)