From patchwork Tue Feb 11 17:49:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11376233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 790CF14B4 for ; Tue, 11 Feb 2020 17:52:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 57A08214DB for ; Tue, 11 Feb 2020 17:52:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581443545; bh=nwuR2uWCcoRqKVX0jc68PcrHdtG3RZH2Nm1tXCXwEfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=cBY+iqO+tNf/ohUTI5IVv2R2I6j9M3Qu/J+DTH31A4TWzxwCJ90tfnVHr6PUiD+YI dSaF/Z+5NG1qCGB6iieAWG2U0OeDaVqNJHoA/z11yYfvwNrVNsd39Yv3QPrp+t5XtK vghxzkgxrvoGbNfjKwvqbPv4sEWf9I/KCeeKqV18= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730539AbgBKRwY (ORCPT ); Tue, 11 Feb 2020 12:52:24 -0500 Received: from mail.kernel.org ([198.145.29.99]:55284 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730525AbgBKRwX (ORCPT ); Tue, 11 Feb 2020 12:52:23 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5480320661; Tue, 11 Feb 2020 17:52:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581443543; bh=nwuR2uWCcoRqKVX0jc68PcrHdtG3RZH2Nm1tXCXwEfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U/dRmCwbsNRjuMAnf0BBQZsTuNSDxWEebKAwTif4CxWRts/CgY25Ak470/qhj6xlf 2OeUtQ036cMaTKpQO0qTSsT+6URFXid05iM9A5df8Kf5HdM1hwO/QL4GfIxr+Cgy9r rURnrtQ0WEETid1RYNhuI1kknJ9j4jLjerZ1PJaQ= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1j1Zg8-004O7k-SI; Tue, 11 Feb 2020 17:50:33 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Andre Przywara , Christoffer Dall , Dave Martin , Jintack Lim , Alexandru Elisei , James Morse , Julien Thierry , Suzuki K Poulose Subject: [PATCH v2 67/94] arm64: Add level-hinted TLB invalidation helper Date: Tue, 11 Feb 2020 17:49:11 +0000 Message-Id: <20200211174938.27809-68-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211174938.27809-1-maz@kernel.org> References: <20200211174938.27809-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com, christoffer.dall@arm.com, Dave.Martin@arm.com, jintack@cs.columbia.edu, alexandru.elisei@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a level-hinted TLB invalidation helper that only gets used if ARMv8.4-TTL gets detected. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index bc3949064725..a3f70778a325 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ +#include #include #include #include @@ -59,6 +60,35 @@ __ta; \ }) +#define TLBI_TTL_MASK GENMASK_ULL(47, 44) + +#define __tlbi_level(op, addr, level) \ + do { \ + u64 arg = addr; \ + \ + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ + level) { \ + u64 ttl = level; \ + \ + switch (PAGE_SIZE) { \ + case SZ_4K: \ + ttl |= 1 << 2; \ + break; \ + case SZ_16K: \ + ttl |= 2 << 2; \ + break; \ + case SZ_64K: \ + ttl |= 3 << 2; \ + break; \ + } \ + \ + arg &= ~TLBI_TTL_MASK; \ + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \ + } \ + \ + __tlbi(op, arg); \ + } while(0) + /* * TLB Invalidation * ================