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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id c2sm13819964wrf.68.2020.12.06.15.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:23 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini , Claudio Fontana Subject: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Date: Mon, 7 Dec 2020 00:39:48 +0100 Message-Id: <20201206233949.3783184-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict the following CPUClass handlers to TCG: - do_interrupt - do_transaction_failed - do_unaligned_access Signed-off-by: Philippe Mathieu-Daudé --- Cc: Claudio Fontana target/mips/cpu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8a4486e3ea1..03bd35b7903 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; - cc->do_interrupt = mips_cpu_do_interrupt; cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = mips_cpu_do_transaction_failed; - cc->do_unaligned_access = mips_cpu_do_unaligned_access; + cc->do_interrupt = mips_cpu_do_interrupt; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->vmsd = &vmstate_mips_cpu; #endif @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) #ifdef CONFIG_TCG cc->tcg_initialize = mips_tcg_init; cc->tlb_fill = mips_cpu_tlb_fill; +#if !defined(CONFIG_USER_ONLY) + cc->do_unaligned_access = mips_cpu_do_unaligned_access; + cc->do_transaction_failed = mips_cpu_do_transaction_failed; +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif cc->gdb_num_core_regs = 73;