diff mbox series

[16/17] target/mips: Introduce decode tree bindings for MSA opcodes

Message ID 20201208003702.4088927-17-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/mips: Convert MSA ASE to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Dec. 8, 2020, 12:37 a.m. UTC 
Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.

We decode the branch instructions, and all instructions based
on the MSA opcode.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h         |  1 +
 target/mips/mod-msa32.decode    | 24 ++++++++++++++++++++++++
 target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
 target/mips/meson.build         |  5 +++++
 4 files changed, 61 insertions(+)
 create mode 100644 target/mips/mod-msa32.decode

Comments

Richard Henderson Dec. 9, 2020, 12:05 a.m. UTC | #1 
On 12/7/20 6:37 PM, Philippe Mathieu-Daudé wrote:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
> 
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h         |  1 +
>  target/mips/mod-msa32.decode    | 24 ++++++++++++++++++++++++
>  target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
>  target/mips/meson.build         |  5 +++++
>  4 files changed, 61 insertions(+)
>  create mode 100644 target/mips/mod-msa32.decode

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Jiaxun Yang Dec. 9, 2020, 4:09 a.m. UTC | #2 
在 2020/12/8 上午8:37, Philippe Mathieu-Daudé 写道:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
>
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Double checked opcode formats with the manual.

Thanks!

- Jiaxun

> ---
>   target/mips/translate.h         |  1 +
>   target/mips/mod-msa32.decode    | 24 ++++++++++++++++++++++++
>   target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
>   target/mips/meson.build         |  5 +++++
>   4 files changed, 61 insertions(+)
>   create mode 100644 target/mips/mod-msa32.decode
>
> diff --git a/target/mips/translate.h b/target/mips/translate.h
> index c26b0d9155d..c4fe18d187e 100644
> --- a/target/mips/translate.h
> +++ b/target/mips/translate.h
> @@ -84,5 +84,6 @@ extern TCGv bcond;
>   void msa_translate_init(void);
>   void gen_msa(DisasContext *ctx);
>   void gen_msa_branch(DisasContext *ctx, uint32_t op1);
> +bool decode_msa32(DisasContext *ctx, uint32_t insn);
>   
>   #endif
> diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
> new file mode 100644
> index 00000000000..d69675132b8
> --- /dev/null
> +++ b/target/mips/mod-msa32.decode
> @@ -0,0 +1,24 @@
> +# MIPS SIMD Architecture Module instruction set
> +#
> +# Copyright (C) 2020  Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference:
> +#       MIPS Architecture for Programmers Volume IV-j
> +#       The MIPS32 SIMD Architecture Module, Revision 1.12
> +#       (Document Number: MD00866-2B-MSA32-AFP-01.12)
> +#
> +
> +&msa_bz             df wt s16
> +
> +@bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
> +@bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
> +
> +BZ_V                010001 01011  ..... ................    @bz
> +BNZ_V               010001 01111  ..... ................    @bz
> +
> +BZ_x                010001 110 .. ..... ................    @bz_df
> +BNZ_x               010001 111 .. ..... ................    @bz_df
> +
> +MSA                 011110 --------------------------
> diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
> index 55c2a2f1acc..02df39c6b6c 100644
> --- a/target/mips/mod-msa_translate.c
> +++ b/target/mips/mod-msa_translate.c
> @@ -6,6 +6,7 @@
>    *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
>    *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
>    *  Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
> + *  Copyright (c) 2020 Philippe Mathieu-Daudé
>    *
>    * SPDX-License-Identifier: LGPL-2.1-or-later
>    */
> @@ -17,6 +18,9 @@
>   #include "fpu_helper.h"
>   #include "internal.h"
>   
> +/* Include the auto-generated decoder.  */
> +#include "decode-mod-msa32.c.inc"
> +
>   #define OPC_MSA (0x1E << 26)
>   
>   #define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
> @@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
>       return true;
>   }
>   
> +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
> +{
> +    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
> +}
> +
> +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
> +{
> +    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
> +}
> +
>   static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
>   {
>       check_msa_access(ctx);
> @@ -391,6 +405,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
>       return true;
>   }
>   
> +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
> +{
> +    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
> +}
> +
> +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
> +{
> +    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
> +}
> +
>   void gen_msa_branch(DisasContext *ctx, uint32_t op1)
>   {
>       uint8_t df = (ctx->opcode >> 21) & 0x3;
> @@ -2264,3 +2288,10 @@ void gen_msa(DisasContext *ctx)
>           break;
>       }
>   }
> +
> +static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
> +{
> +    gen_msa(ctx);
> +
> +    return true;
> +}
> diff --git a/target/mips/meson.build b/target/mips/meson.build
> index b6697e2fd72..7d0414bbe23 100644
> --- a/target/mips/meson.build
> +++ b/target/mips/meson.build
> @@ -1,4 +1,9 @@
> +gen = [
> +  decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
> +]
> +
>   mips_ss = ss.source_set()
> +mips_ss.add(gen)
>   mips_ss.add(files(
>     'cpu.c',
>     'dsp_helper.c',
diff mbox series

Patch

diff --git a/target/mips/translate.h b/target/mips/translate.h
index c26b0d9155d..c4fe18d187e 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -84,5 +84,6 @@  extern TCGv bcond;
 void msa_translate_init(void);
 void gen_msa(DisasContext *ctx);
 void gen_msa_branch(DisasContext *ctx, uint32_t op1);
+bool decode_msa32(DisasContext *ctx, uint32_t insn);
 
 #endif
diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
new file mode 100644
index 00000000000..d69675132b8
--- /dev/null
+++ b/target/mips/mod-msa32.decode
@@ -0,0 +1,24 @@ 
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+#       MIPS Architecture for Programmers Volume IV-j
+#       The MIPS32 SIMD Architecture Module, Revision 1.12
+#       (Document Number: MD00866-2B-MSA32-AFP-01.12)
+#
+
+&msa_bz             df wt s16
+
+@bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
+@bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
+
+BZ_V                010001 01011  ..... ................    @bz
+BNZ_V               010001 01111  ..... ................    @bz
+
+BZ_x                010001 110 .. ..... ................    @bz_df
+BNZ_x               010001 111 .. ..... ................    @bz_df
+
+MSA                 011110 --------------------------
diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
index 55c2a2f1acc..02df39c6b6c 100644
--- a/target/mips/mod-msa_translate.c
+++ b/target/mips/mod-msa_translate.c
@@ -6,6 +6,7 @@ 
  *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
  *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
  *  Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ *  Copyright (c) 2020 Philippe Mathieu-Daudé
  *
  * SPDX-License-Identifier: LGPL-2.1-or-later
  */
@@ -17,6 +18,9 @@ 
 #include "fpu_helper.h"
 #include "internal.h"
 
+/* Include the auto-generated decoder.  */
+#include "decode-mod-msa32.c.inc"
+
 #define OPC_MSA (0x1E << 26)
 
 #define MASK_MSA_MINOR(op)          (MASK_OP_MAJOR(op) | (op & 0x3F))
@@ -370,6 +374,16 @@  static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
     return true;
 }
 
+static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+}
+
+static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+    return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+}
+
 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
 {
     check_msa_access(ctx);
@@ -391,6 +405,16 @@  static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
     return true;
 }
 
+static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+}
+
+static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+    return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+}
+
 void gen_msa_branch(DisasContext *ctx, uint32_t op1)
 {
     uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -2264,3 +2288,10 @@  void gen_msa(DisasContext *ctx)
         break;
     }
 }
+
+static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
+{
+    gen_msa(ctx);
+
+    return true;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index b6697e2fd72..7d0414bbe23 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,9 @@ 
+gen = [
+  decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
+]
+
 mips_ss = ss.source_set()
+mips_ss.add(gen)
 mips_ss.add(files(
   'cpu.c',
   'dsp_helper.c',