[PULL,10/26] target/mips: Explicit Release 6 MMU types

Message ID	20201213201946.236123-11-f4bug@amsat.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@kernel.org> Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philippe.mathieu.daude@gmail.com> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Paolo Bonzini <pbonzini@redhat.com>, Aurelien Jarno <aurelien@aurel32.net>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, kvm@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>, Huacai Chen <chenhuacai@kernel.org>, Paul Burton <paulburton@kernel.org>, Richard Henderson <richard.henderson@linaro.org> Subject: [PULL 10/26] target/mips: Explicit Release 6 MMU types Date: Sun, 13 Dec 2020 21:19:30 +0100 Message-Id: <20201213201946.236123-11-f4bug@amsat.org> In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[PULL,01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org \| expand [PULL,01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org [PULL,02/26] target/mips/kvm: Assert unreachable code is not used [PULL,03/26] target/mips/kvm: Remove unused headers [PULL,04/26] target/mips: Include "exec/memattrs.h" in 'internal.h' [PULL,05/26] target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MIN [PULL,06/26] target/mips: Do not include CP0 helpers in user-mode emulation [PULL,07/26] target/mips: Remove unused headers from cp0_helper.c [PULL,08/26] target/mips: Also display exception names in user-mode [PULL,09/26] target/mips: Allow executing MSA instructions on Loongson-3A4000 [PULL,10/26] target/mips: Explicit Release 6 MMU types [PULL,11/26] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() [PULL,12/26] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument [PULL,13/26] hw/mips: Move address translation helpers to target/mips/ [PULL,14/26] target/mips: Remove unused headers from translate.c [PULL,15/26] target/mips: Remove unused headers from op_helper.c [PULL,16/26] target/mips: Remove mips_def_t unused argument from mvp_init() [PULL,17/26] target/mips: Introduce ase_mt_available() helper [PULL,18/26] target/mips: Do not initialize MT registers if MT ASE absent [PULL,19/26] hw/mips/malta: Do not initialize MT registers if MT ASE absent [PULL,20/26] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit() [PULL,21/26] target/mips: Extract cpu_supports/cpu_set translate.c [PULL,22/26] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c [PULL,23/26] target/mips: Move cpu definitions, reset() and realize() to cpu.c [PULL,24/26] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() [PULL,25/26] target/mips: Remove unused headers from fpu_helper.c [PULL,26/26] target/mips: Use FloatRoundMode enum for FCR31 modes conversion

Message ID

20201213201946.236123-11-f4bug@amsat.org (mailing list archive)

State

New, archived

Headers

Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=
  <philippe.mathieu.daude@gmail.com>
From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>,
 Paolo Bonzini <pbonzini@redhat.com>, Aurelien Jarno <aurelien@aurel32.net>,
 Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, kvm@vger.kernel.org,
 Jiaxun Yang <jiaxun.yang@flygoat.com>, Huacai Chen <chenhuacai@kernel.org>,
 Paul Burton <paulburton@kernel.org>,
 Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 10/26] target/mips: Explicit Release 6 MMU types
Date: Sun, 13 Dec 2020 21:19:30 +0100
Message-Id: <20201213201946.236123-11-f4bug@amsat.org>
In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org>
References: <20201213201946.236123-1-f4bug@amsat.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

[PULL,01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org | expand

Commit Message

Philippe Mathieu-Daudé Dec. 13, 2020, 8:19 p.m. UTC

As of Release 6, MMU type 4 is assigned to "Dual Variable-Page-Size
and Fixed-Page-Size TLBs" and type 2 to "Block Address Translation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-4-f4bug@amsat.org>
---
 target/mips/internal.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 76b7a85cbb3..bcd3d857ab6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -16,10 +16,11 @@ 
  * CP0C0_MT field.
  */
 enum mips_mmu_types {
-    MMU_TYPE_NONE,
-    MMU_TYPE_R4000,
-    MMU_TYPE_RESERVED,
-    MMU_TYPE_FMT,
+    MMU_TYPE_NONE       = 0,
+    MMU_TYPE_R4000      = 1,    /* Standard TLB */
+    MMU_TYPE_BAT        = 2,    /* Block Address Translation */
+    MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
+    MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
     MMU_TYPE_R3000,
     MMU_TYPE_R6000,
     MMU_TYPE_R8000

[PULL,10/26] target/mips: Explicit Release 6 MMU types

Commit Message

Patch