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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id j15sm28136891wrr.85.2020.12.13.12.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:48 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 12/26] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument Date: Sun, 13 Dec 2020 21:19:32 +0100 Message-Id: <20201213201946.236123-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce cpu_supports_isa() which takes a CPUMIPSState argument, more useful at runtime when the CPU is created (no need to call the extensive object_class_by_name()). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-3-f4bug@amsat.org> --- target/mips/cpu.h | 1 + target/mips/cpu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c65c87bf99..e8bca75f237 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b42..687e2680dd1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) return MIPS_CPU(cpu); } + +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) +{ + return (env->cpu_model->insn_flags & isa_mask) != 0; +}