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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id e16sm31304940wra.94.2020.12.13.12.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:48 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 24/26] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Date: Sun, 13 Dec 2020 21:19:44 +0100 Message-Id: <20201213201946.236123-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-17-f4bug@amsat.org> --- target/mips/cpu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f2c4de7d070..aadc6f8e74d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,17 +104,6 @@ static bool mips_cpu_has_work(CPUState *cs) #include "translate_init.c.inc" -static void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env); -} - /* TODO QOM'ify CPU reset and remove */ static void cpu_state_reset(CPUMIPSState *env) { @@ -400,6 +389,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); MIPSCPU *cpu = MIPS_CPU(dev); + CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -423,7 +413,13 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) return; } - cpu_mips_realize_env(&cpu->env); + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env); cpu_reset(cs); qemu_init_vcpu(cs);