diff mbox series

[PULL,34/66] target/mips: Only build TCG code when CONFIG_TCG is set

Message ID 20210107222253.20382-35-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA | expand

Commit Message

Philippe Mathieu-Daudé Jan. 7, 2021, 10:22 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
---
 target/mips/meson.build | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5a49951c6d7..596eb1aeeb3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,9 +1,11 @@ 
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'gdbstub.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
   'dsp_helper.c',
   'fpu_helper.c',
-  'gdbstub.c',
   'lmmi_helper.c',
   'msa_helper.c',
   'op_helper.c',
@@ -15,11 +17,13 @@ 
 mips_softmmu_ss = ss.source_set()
 mips_softmmu_ss.add(files(
   'addr.c',
-  'cp0_helper.c',
   'cp0_timer.c',
   'machine.c',
   'mips-semi.c',
 ))
+mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'cp0_helper.c',
+))
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}