diff mbox series

[PULL,03/66] target/mips/addr: Add translation helpers for KSEG1

Message ID 20210107222253.20382-4-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA | expand

Commit Message

Philippe Mathieu-Daudé Jan. 7, 2021, 10:21 p.m. UTC
From: Jiaxun Yang <jiaxun.yang@flygoat.com>

It's useful for bootloader to do I/O operations.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h  |  2 ++
 target/mips/addr.c | 10 ++++++++++
 2 files changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 0086f95ea2a..0c2d397e4a9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1312,6 +1312,8 @@  uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
 
 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
 bool mips_um_ksegs_enabled(void);
 void mips_um_ksegs_enable(void);
 
diff --git a/target/mips/addr.c b/target/mips/addr.c
index 27a6036c451..86f1c129c9f 100644
--- a/target/mips/addr.c
+++ b/target/mips/addr.c
@@ -40,6 +40,16 @@  uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
     return addr | 0x40000000ll;
 }
 
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr)
+{
+    return addr & 0x1fffffffll;
+}
+
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr)
+{
+    return (addr & 0x1fffffffll) | 0xffffffffa0000000ll;
+}
+
 bool mips_um_ksegs_enabled(void)
 {
     return mips_um_ksegs;