@@ -162,4 +162,7 @@ extern TCGv bcond;
} \
} while (0)
+/* MSA */
+void msa_translate_init(void);
+
#endif
@@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
+void msa_translate_init(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
+ /*
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
+ */
+ msa_wr_d[i * 2] = fpu_f64[i];
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ }
+}
+
void mips_tcg_init(void)
{
int i;
@@ -31566,20 +31584,7 @@ void mips_tcg_init(void)
fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
}
- /* MSA */
- for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
-
- /*
- * The MSA vector registers are mapped on the
- * scalar floating-point unit (FPU) registers.
- */
- msa_wr_d[i * 2] = fpu_f64[i];
- off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
- msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
- }
-
+ msa_translate_init();
cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {