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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id q15sm9908485wrw.75.2021.01.07.14.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:49 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code Date: Thu, 7 Jan 2021 23:22:44 +0100 Message-Id: <20210107222253.20382-58-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-6-f4bug@amsat.org> --- target/mips/translate.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cd34b06faae..f4481afb8de 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -280,9 +280,6 @@ enum { R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, R6_OPC_DCLO = 0x13 | OPC_SPECIAL, R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, - - OPC_LSA = 0x05 | OPC_SPECIAL, - OPC_DLSA = 0x15 | OPC_SPECIAL, }; /* Multiplication variants of the vr54xx. */ @@ -24319,9 +24316,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL(ctx->opcode); switch (op1) { - case OPC_LSA: - gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case OPC_MULT: case OPC_MULTU: case OPC_DIV: @@ -24372,10 +24366,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DLSA: - check_mips_64(ctx); - gen_DLSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case R6_OPC_DCLO: case R6_OPC_DCLZ: if (rt == 0 && sa == 1) { @@ -24637,18 +24627,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, ISA_MIPS2); gen_trap(ctx, op1, rs, rt, -1); break; - case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } else { - /* Pmon entry point, also R4010 selsl */ + case OPC_PMON: + /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD - MIPS_INVAL("PMON / selsl"); - gen_reserved_instruction(ctx); + MIPS_INVAL("PMON / selsl"); + gen_reserved_instruction(ctx); #else - gen_helper_0e0i(pmon, sa); + gen_helper_0e0i(pmon, sa); #endif - } break; case OPC_SYSCALL: generate_exception_end(ctx, EXCP_SYSCALL); @@ -24739,11 +24725,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; } break; - case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } - break; #endif default: if (ctx->insn_flags & ISA_MIPS_R6) {