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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id r20sm9154498wmh.15.2021.01.07.14.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:04 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:47 +0100 Message-Id: <20210107222253.20382-61-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-9-f4bug@amsat.org> --- target/mips/mips32r6.decode | 3 +++ target/mips/translate.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 7b12a1bff25..e3b3934539a 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -19,3 +19,6 @@ LSA 000000 ..... ..... ..... 000 .. 000101 @lsa REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 + +REMOVED 101111 ----- ----- ---------------- # CACHE +REMOVED 110011 ----- ----- ---------------- # PREF diff --git a/target/mips/translate.c b/target/mips/translate.c index 52397bce84b..e8389738c57 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28620,7 +28620,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -28629,7 +28628,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else {