| Message ID | 20210126134202.381996-4-wangyanan55@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable CPU TTRem feature for stage-2 | expand |
diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 4d177ce1d536..c8b959e3951b 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -437,6 +437,7 @@ struct stage2_map_data { struct kvm_s2_mmu *mmu; struct kvm_mmu_memory_cache *memcache; + u32 ttrem_level; }; static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, @@ -633,6 +634,7 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, .phys = ALIGN_DOWN(phys, PAGE_SIZE), .mmu = pgt->mmu, .memcache = mc, + .ttrem_level = system_support_level_of_ttrem(), }; struct kvm_pgtable_walker walker = { .cb = stage2_map_walker,
As TTrem can be used when coalesce existing table mappings into a block in guest stage-2 translation, so just support usage of it. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> --- arch/arm64/kvm/hyp/pgtable.c | 2 ++ 1 file changed, 2 insertions(+)