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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id w25sm12591514wmc.42.2021.01.29.17.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:00 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:22 +0100 Message-Id: <20210130015227.4071332-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A KVM-only build won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F The following machine is no more built when TCG is disabled: - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/aarch64-softmmu.mak | 1 - hw/arm/Kconfig | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak index 958b1e08e40..a4202f56817 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -CONFIG_XLNX_ZYNQMP_ARM=y CONFIG_XLNX_VERSAL=y CONFIG_SBSA_REF=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index daab7081994..320428bf97e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -11,6 +11,11 @@ config ARM_V6 depends on TCG select ARM_COMPATIBLE_SEMIHOSTING +config ARM_V7R + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + config ARM_VIRT bool imply PCI_DEVICES @@ -377,8 +382,10 @@ config STM32F405_SOC config XLNX_ZYNQMP_ARM bool + default y if TCG select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD