@@ -48,3 +48,8 @@ unsigned long long get_amd_sev_c_bit_mask(void)
{
return 1ull << amd_sev_c_bit_pos;
}
+
+unsigned long long get_amd_sev_c_bit_pos(void)
+{
+ return amd_sev_c_bit_pos;
+}
@@ -37,5 +37,6 @@
EFI_STATUS setup_amd_sev(void);
unsigned long long get_amd_sev_c_bit_mask(void);
+unsigned long long get_amd_sev_c_bit_pos(void);
#endif /* _X86_AMD_SEV_H_ */
@@ -33,10 +33,19 @@ typedef unsigned long pgd_t;
#define PT_PAGE_SIZE_MASK (1ull << 7)
#define PT_GLOBAL_MASK (1ull << 8)
#define PT64_NX_MASK (1ull << 63)
-#define PT_ADDR_MASK GENMASK_ULL(51, 12)
+#ifndef CONFIG_AMD_SEV
+#define PT_ADDR_UPPER_BOUND (51)
+#else
+/* lib/x86/amd_sev.c */
+extern unsigned long long get_amd_sev_c_bit_mask(void);
+extern unsigned long long get_amd_sev_c_bit_pos(void);
+#define PT_ADDR_UPPER_BOUND (get_amd_sev_c_bit_pos()-1)
+#endif /* CONFIG_AMD_SEV */
+#define PT_ADDR_LOWER_BOUND (PAGE_SHIFT)
+#define PT_ADDR_MASK GENMASK_ULL(PT_ADDR_UPPER_BOUND, PT_ADDR_LOWER_BOUND)
#define PDPTE64_PAGE_SIZE_MASK (1ull << 7)
-#define PDPTE64_RSVD_MASK GENMASK_ULL(51, cpuid_maxphyaddr())
+#define PDPTE64_RSVD_MASK GENMASK_ULL(PT_ADDR_UPPER_BOUND, cpuid_maxphyaddr())
#define PT_AD_MASK (PT_ACCESSED_MASK | PT_DIRTY_MASK)
@@ -26,6 +26,9 @@ pteval_t *install_pte(pgd_t *cr3,
pt_page = 0;
memset(new_pt, 0, PAGE_SIZE);
pt[offset] = virt_to_phys(new_pt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | pte_opt_mask;
+#ifdef CONFIG_AMD_SEV
+ pt[offset] |= get_amd_sev_c_bit_mask();
+#endif /* CONFIG_AMD_SEV */
}
pt = phys_to_virt(pt[offset] & PT_ADDR_MASK);
}
@@ -63,7 +66,7 @@ struct pte_search find_pte_level(pgd_t *cr3, void *virt,
if (r.level == lowest_level)
return r;
- pt = phys_to_virt(pte & 0xffffffffff000ull);
+ pt = phys_to_virt(pte & PT_ADDR_MASK);
}
}
@@ -94,13 +97,20 @@ pteval_t *get_pte_level(pgd_t *cr3, void *virt, int pte_level)
pteval_t *install_large_page(pgd_t *cr3, phys_addr_t phys, void *virt)
{
- return install_pte(cr3, 2, virt,
- phys | PT_PRESENT_MASK | PT_WRITABLE_MASK | pte_opt_mask | PT_PAGE_SIZE_MASK, 0);
+ phys_addr_t flags = PT_PRESENT_MASK | PT_WRITABLE_MASK | pte_opt_mask | PT_PAGE_SIZE_MASK;
+#ifdef CONFIG_AMD_SEV
+ flags |= get_amd_sev_c_bit_mask();
+#endif /* CONFIG_AMD_SEV */
+ return install_pte(cr3, 2, virt, phys | flags, 0);
}
pteval_t *install_page(pgd_t *cr3, phys_addr_t phys, void *virt)
{
- return install_pte(cr3, 1, virt, phys | PT_PRESENT_MASK | PT_WRITABLE_MASK | pte_opt_mask, 0);
+ phys_addr_t flags = PT_PRESENT_MASK | PT_WRITABLE_MASK | pte_opt_mask;
+#ifdef CONFIG_AMD_SEV
+ flags |= get_amd_sev_c_bit_mask();
+#endif /* CONFIG_AMD_SEV */
+ return install_pte(cr3, 1, virt, phys | flags, 0);
}
void install_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt)
AMD SEV introduces c-bit to page table entries. To work with AMD SEV: 1. c-bit should be set for new page table entries 2. address calculation should not use c-bit as part of address Signed-off-by: Zixuan Wang <zixuanwang@google.com> --- lib/x86/amd_sev.c | 5 +++++ lib/x86/amd_sev.h | 1 + lib/x86/asm/page.h | 13 +++++++++++-- lib/x86/vm.c | 18 ++++++++++++++---- 4 files changed, 31 insertions(+), 6 deletions(-)