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Tue, 31 Aug 2021 03:07:32 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 Aug 2021 20:07:31 -0700 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 31 Aug 2021 03:07:31 +0000 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [RFC][PATCH v2 08/13] iommu/arm-smmu-v3: Add VMID alloc/free helpers Date: Mon, 30 Aug 2021 19:59:18 -0700 Message-ID: <20210831025923.15812-9-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210831025923.15812-1-nicolinc@nvidia.com> References: <20210831025923.15812-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5ee3b801-5141-4d08-3af7-08d96c2c79f0 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0235: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 03:07:32.8094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ee3b801-5141-4d08-3af7-08d96c2c79f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0235 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org NVIDIA implementation needs to link its Virtual Interface to a VMID, before a device gets attached to the corresponding iommu domain. One way to ensure that is to allocate a VMID from impl side and to pass it down to virtual machine hypervisor so that later it can set it back to passthrough devices' iommu domains calling newly added arm_smmu_set/get_nesting_vmid() functions. This patch adds a pair of helpers to allocate and free VMID in the bitmap. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c0ae117711fa..497d55ec659b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2032,6 +2032,16 @@ static void arm_smmu_bitmap_free(unsigned long *map, int idx) clear_bit(idx, map); } +int arm_smmu_vmid_alloc(struct arm_smmu_device *smmu) +{ + return arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); +} + +void arm_smmu_vmid_free(struct arm_smmu_device *smmu, u16 vmid) +{ + arm_smmu_bitmap_free(smmu->vmid_map, vmid); +} + static void arm_smmu_domain_free(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ea2c61d52df8..20463d17fd9f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -749,6 +749,9 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, unsigned long iova, size_t size); +int arm_smmu_vmid_alloc(struct arm_smmu_device *smmu); +void arm_smmu_vmid_free(struct arm_smmu_device *smmu, u16 vmid); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);