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(163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id y24sm2479386wma.9.2021.09.02.09.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:16:46 -0700 (PDT) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 10/30] target/avr: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:23 +0200 Message-Id: <20210902161543.417092-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/avr/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e9fa54c9777..6267cc6d530 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -32,6 +32,7 @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc_w = value / 2; /* internally PC points to words */ } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool avr_cpu_has_work(CPUState *cs) { AVRCPU *cpu = AVR_CPU(cs); @@ -40,6 +41,7 @@ static bool avr_cpu_has_work(CPUState *cs) return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) && cpu_interrupts_enabled(env); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) @@ -198,6 +200,7 @@ static const struct TCGCPUOps avr_tcg_ops = { .tlb_fill = avr_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = avr_cpu_has_work, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .do_interrupt = avr_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -214,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; - cc->has_work = avr_cpu_has_work; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->memory_rw_debug = avr_cpu_memory_rw_debug;