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(163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id c3sm2410025wrd.34.2021.09.02.09.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:17:11 -0700 (PDT) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 14/30] target/i386: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:27 +0200 Message-Id: <20210902161543.417092-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.c | 6 ------ target/i386/tcg/tcg-cpu.c | 8 +++++++- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 04f59043804..b7417d29f44 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6548,11 +6548,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) return 0; } -static bool x86_cpu_has_work(CPUState *cs) -{ - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); @@ -6757,7 +6752,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; - cc->has_work = x86_cpu_has_work; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->gdb_read_register = x86_cpu_gdb_read_register; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index fd86daf93d2..6cde53603ba 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -55,6 +55,11 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } #ifndef CONFIG_USER_ONLY +static bool x86_cpu_has_work(CPUState *cs) +{ + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; +} + static bool x86_debug_check_breakpoint(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); @@ -63,7 +68,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } -#endif +#endif /* CONFIG_USER_ONLY */ #include "hw/core/tcg-cpu-ops.h" @@ -76,6 +81,7 @@ static const struct TCGCPUOps x86_tcg_ops = { #ifdef CONFIG_USER_ONLY .fake_user_exception = x86_cpu_do_interrupt, #else + .has_work = x86_cpu_has_work, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler,