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(163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id f18sm2080257wmc.6.2021.09.02.09.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:17:26 -0700 (PDT) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 16/30] target/microblaze: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:29 +0200 Message-Id: <20210902161543.417092-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925f..74fbb5d201a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -92,12 +92,15 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } +#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_TCG static bool mb_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +#endif /* CONFIG_TCG */ -#ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { MicroBlazeCPU *cpu = opaque; @@ -142,7 +145,7 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) cpu_reset_interrupt(cs, type); } } -#endif +#endif /* !CONFIG_USER_ONLY */ static void mb_cpu_reset(DeviceState *dev) { @@ -368,6 +371,7 @@ static const struct TCGCPUOps mb_tcg_ops = { .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = mb_cpu_has_work, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, @@ -386,8 +390,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; - cc->has_work = mb_cpu_has_work; - cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register;