From patchwork Tue Oct 12 04:35:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12551367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 828B0C433FE for ; Tue, 12 Oct 2021 04:36:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CC0861040 for ; Tue, 12 Oct 2021 04:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232435AbhJLEib (ORCPT ); Tue, 12 Oct 2021 00:38:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232374AbhJLEia (ORCPT ); Tue, 12 Oct 2021 00:38:30 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 056BBC061570 for ; Mon, 11 Oct 2021 21:36:30 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id m9-20020a17090ade09b029017903cc8d6cso882899pjv.4 for ; Mon, 11 Oct 2021 21:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=nTXMtA3D4TOs62yx9xXmosWMy1vxPMYLyf89zj4P3sg=; b=DrM5WEJPxxLwrWWTHYAj8Qc4xV1msbr3ZUUIz+Vgg9CThMSACYyczJ1UDERNSK6Ggi oQ1MytUagNqi0alUFD2TBfQHxcb/biUjA9kU3iUrAkSkECbDozt/+ZHlOM2vIMgDe9DU xnCxdoFjVo+srhzN1SSDvIGsxKNr5p6kS/QEdy9M/mC+bcmA2HauNgHXrv7L/yShq/FW 9+CVeX4qwbX1/3Vpkveb9m3MH0vBJ1z79pzJh+E/UumcChjyMGgSgu86T5Y5nhHt0Gm/ YYSE3P8dAWvEZkJPNtplpVhxEpAPiOCT0+snPnaL7fQLiew9mZ19iajPqb9Fb8nQRLcu dJTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=nTXMtA3D4TOs62yx9xXmosWMy1vxPMYLyf89zj4P3sg=; b=GyrMf54MOaGugKKrxnorqOi5OC747IGYriQM5DY4NREzX1eate7KGhJLGEZdCcJ3Zr O3OLHjZZ3AiaUoQ47hcaCelXbINwuoxhhsdC2kEEhiDYlYbDemFEZ2P3tsB5eBzM4BrX EupYPaQEaj9NFENGA0g8x+jy0v81YW3p5/hGrB91gXPgZvtZUhbumFc/0kWAiFhfZAfb cfVipXhG7tIyEnSzYjAc9ArZwDNMx8SokyMmPXDMqFvhqnDiDfrjVSYjHZVOXtN0R+BM 5BtiTZn1Qmq3qhb7WseYoS900Y+V0U/JRx0j+DhiJTSItbK8CN5HHW20A7fKuN419hgU lTHw== X-Gm-Message-State: AOAM5322EkV63pRMvxhHxvnUw+YBfrcZSNSWa3ExJoNlY5vw4BJWHki8 CdcxSLsI1zymBKzCA+HvHB4FaENqwm0= X-Google-Smtp-Source: ABdhPJxUJvThrtjbXZAeg5X6W4utelZnX4+QN62pfB876yK1oZAkUxR/X7DkF7nkuOQxW5rPD2nt286kpBA= X-Received: from reiji-vws.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:15a3]) (user=reijiw job=sendgmr) by 2002:a17:90b:3b44:: with SMTP id ot4mr3486235pjb.145.1634013389503; Mon, 11 Oct 2021 21:36:29 -0700 (PDT) Date: Mon, 11 Oct 2021 21:35:17 -0700 In-Reply-To: <20211012043535.500493-1-reijiw@google.com> Message-Id: <20211012043535.500493-8-reijiw@google.com> Mime-Version: 1.0 References: <20211012043535.500493-1-reijiw@google.com> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog Subject: [RFC PATCH 07/25] KVM: arm64: Make ID_AA64PFR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch adds id_reg_info for ID_AA64PFR1_EL1 to make it writable by userspace. Return an error if userspace tries to set MTE field of the register to a value that conflicts with KVM_CAP_ARM_MTE configuration for the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 51 ++++++++++++++++++++++++++------- 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b268082d67ed..aa0692595122 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -793,6 +793,7 @@ #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 /* id_aa64pfr1 */ +#define ID_AA64PFR1_CSV2FRAC_SHIFT 32 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 #define ID_AA64PFR1_RASFRAC_SHIFT 12 #define ID_AA64PFR1_MTE_SHIFT 8 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 63eb207b387f..0e4423a81cb9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -314,6 +314,20 @@ static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, u64 val) return 0; } +static int validate_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, u64 val) +{ + bool kvm_mte = kvm_has_mte(vcpu->kvm); + unsigned int mte; + + mte = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR1_MTE_SHIFT); + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT. */ + if (kvm_mte ^ (mte > 0)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) { u64 limit; @@ -341,6 +355,14 @@ static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) id_reg->vcpu_limit_val = limit; } +static void init_id_aa64pfr1_el1_info(struct id_reg_info *id_reg) +{ + id_reg->sys_val = read_sanitised_ftr_reg(id_reg->sys_reg); + id_reg->vcpu_limit_val = (system_supports_mte() ? + id_reg->sys_val : + (id_reg->sys_val & ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE))); +} + static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, struct id_reg_info *idr) { @@ -349,6 +371,14 @@ static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64PFR0_SVE))); } +static u64 get_reset_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, + struct id_reg_info *idr) +{ + return kvm_has_mte(vcpu->kvm) ? + idr->vcpu_limit_val : + (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE))); +} + static struct id_reg_info id_aa64pfr0_el1_info = { .sys_reg = SYS_ID_AA64PFR0_EL1, .init = init_id_aa64pfr0_el1_info, @@ -356,6 +386,16 @@ static struct id_reg_info id_aa64pfr0_el1_info = { .get_reset_val = get_reset_id_aa64pfr0_el1, }; +static struct id_reg_info id_aa64pfr1_el1_info = { + .sys_reg = SYS_ID_AA64PFR1_EL1, + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC), + .init = init_id_aa64pfr1_el1_info, + .validate = validate_id_aa64pfr1_el1, + .get_reset_val = get_reset_id_aa64pfr1_el1, +}; + /* * An ID register that needs special handling to control the value for the * guest must have its own id_reg_info in id_reg_info_table. @@ -366,6 +406,7 @@ static struct id_reg_info id_aa64pfr0_el1_info = { #define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)]) static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, + [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, }; static int validate_id_reg(struct kvm_vcpu *vcpu, @@ -1202,16 +1243,6 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, u64 val = raz ? 0 : __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)); switch (id) { - case SYS_ID_AA64PFR1_EL1: - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); - if (kvm_has_mte(vcpu->kvm)) { - u64 pfr, mte; - - pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); - mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte); - } - break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |