@@ -793,6 +793,7 @@
#define ID_AA64PFR0_ELx_32BIT_64BIT 0x2
/* id_aa64pfr1 */
+#define ID_AA64PFR1_CSV2FRAC_SHIFT 32
#define ID_AA64PFR1_MPAMFRAC_SHIFT 16
#define ID_AA64PFR1_RASFRAC_SHIFT 12
#define ID_AA64PFR1_MTE_SHIFT 8
@@ -422,6 +422,21 @@ static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
return 0;
}
+static int validate_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
+ const struct id_reg_info *id_reg, u64 val)
+{
+ bool kvm_mte = kvm_has_mte(vcpu->kvm);
+ unsigned int mte;
+
+ mte = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR1_MTE_SHIFT);
+
+ /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT. */
+ if (kvm_mte ^ (mte > 0))
+ return -EPERM;
+
+ return 0;
+}
+
static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
{
u64 limit = id_reg->vcpu_limit_val;
@@ -446,6 +461,12 @@ static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
id_reg->vcpu_limit_val = limit;
}
+static void init_id_aa64pfr1_el1_info(struct id_reg_info *id_reg)
+{
+ if (!system_supports_mte())
+ id_reg->vcpu_limit_val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
+}
+
static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
const struct id_reg_info *idr)
{
@@ -454,6 +475,14 @@ static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
(idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64PFR0_SVE)));
}
+static u64 get_reset_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
+ const struct id_reg_info *idr)
+{
+ return kvm_has_mte(vcpu->kvm) ?
+ idr->vcpu_limit_val :
+ (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE)));
+}
+
static struct id_reg_info id_aa64pfr0_el1_info = {
.sys_reg = SYS_ID_AA64PFR0_EL1,
.ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) |
@@ -463,6 +492,16 @@ static struct id_reg_info id_aa64pfr0_el1_info = {
.get_reset_val = get_reset_id_aa64pfr0_el1,
};
+static struct id_reg_info id_aa64pfr1_el1_info = {
+ .sys_reg = SYS_ID_AA64PFR1_EL1,
+ .ftr_check_types = U_FCT(ID_AA64PFR1_RASFRAC_SHIFT, FCT_IGNORE) |
+ U_FCT(ID_AA64PFR1_MPAMFRAC_SHIFT, FCT_IGNORE) |
+ U_FCT(ID_AA64PFR1_CSV2FRAC_SHIFT, FCT_IGNORE),
+ .init = init_id_aa64pfr1_el1_info,
+ .validate = validate_id_aa64pfr1_el1,
+ .get_reset_val = get_reset_id_aa64pfr1_el1,
+};
+
/*
* An ID register that needs special handling to control the value for the
* guest must have its own id_reg_info in id_reg_info_table.
@@ -473,6 +512,7 @@ static struct id_reg_info id_aa64pfr0_el1_info = {
#define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)])
static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info,
+ [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info,
};
static int validate_id_reg(struct kvm_vcpu *vcpu,
@@ -1307,16 +1347,6 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
u64 val = raz ? 0 : __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id));
switch (id) {
- case SYS_ID_AA64PFR1_EL1:
- val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
- if (kvm_has_mte(vcpu->kvm)) {
- u64 pfr, mte;
-
- pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
- mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
- }
- break;
case SYS_ID_AA64ISAR1_EL1:
if (!vcpu_has_ptrauth(vcpu))
val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
This patch adds id_reg_info for ID_AA64PFR1_EL1 to make it writable by userspace. Return an error if userspace tries to set MTE field of the register to a value that conflicts with KVM_CAP_ARM_MTE configuration for the guest. Skip fractional feature fields validation at present and they will be handled by the following patches. Signed-off-by: Reiji Watanabe <reijiw@google.com> --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 50 ++++++++++++++++++++++++++------- 2 files changed, 41 insertions(+), 10 deletions(-)