From patchwork Thu Jan 6 04:26:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12705092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A8AC43217 for ; Thu, 6 Jan 2022 04:28:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232917AbiAFE2i (ORCPT ); Wed, 5 Jan 2022 23:28:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232850AbiAFE2i (ORCPT ); Wed, 5 Jan 2022 23:28:38 -0500 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A9D9C061245 for ; Wed, 5 Jan 2022 20:28:38 -0800 (PST) Received: by mail-pg1-x54a.google.com with SMTP id p28-20020a63951c000000b0033f7b94305dso869310pgd.11 for ; Wed, 05 Jan 2022 20:28:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=qd73lKkEwp4pXgOEovTQqkO4qsQJst+kertasctVO0I=; b=htuin5WXm7Rrpou/vBLh0txyP8bbdWdjvGAzpt7dGMTaglBii2BAZRNBcTX4/Sx8zw BIaEGmC1AaCc7yM2qbyOC3yW3tRYi7/kBwck/5l+nu0uL6n3LGm0ATjW3tTCrfGI4yij /q8BhmPS+QF9KY5ml3EZ4179v13mJK3hQkiYWa1LDLgjhgwCWt0U17JxUVEd9086z2kL 43YP5SuMRB2kvm5wFwGb1aErOAF08R4qEzTi8TWWytolOVLKRt2pz5yDN9x7aqXEzERZ ABpg4yqgt9gAmvxW+GJ05wFv6hJvDSz9cVt+fL6VgNkvRvzLxUoBH5pCmNmU0jmlaQCO 5fOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=qd73lKkEwp4pXgOEovTQqkO4qsQJst+kertasctVO0I=; b=0GlXj/W7ielL6gELLgIdRw4os+WZNMyWmOhuTwRk1SERBpmSYNXievnL9SZBiy0SAM VOe8BfQrK2KMCArLhJbTvZXBWe2JwPgT7UYI4dq9gZZBMpl/ed0vhwxUlN8N6GAEfwWA zTExdnbL/eYuJ6Z/XU2B3zher+us1t6uO7Bv5lcvab1vQgA+PvpUFwLcExYWoToGcBdk syRZSSNpTfIHQHMQvROnURXSE2fptOgMNO035v+zWRFUwatnrPK6BxFughxc76EKOXq5 y/OX3VYSs4Mv/nyDYpdlYf6i+QBYPMHGHhWbAF6Kmp8B2oOUT/8d5GmVVroAeKzD15Xm h7Ww== X-Gm-Message-State: AOAM533Ay3q8PqfmhkyrM7ZSS2rUfvzdyWKvYEdhNr0rgJ+H7ctwbQnd Ugkv6RzUZZALgDUwJeM4+CBQiLNr828= X-Google-Smtp-Source: ABdhPJxuGlf1H5nhDbfEXwbJ81sUGxMyi6/4UT0GpUOgBmgL39/uLHiDysLu3tr0d7MZS7QmSmZsev2JGRc= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:903:2444:b0:149:2f0f:e466 with SMTP id l4-20020a170903244400b001492f0fe466mr56984109pls.145.1641443317545; Wed, 05 Jan 2022 20:28:37 -0800 (PST) Date: Wed, 5 Jan 2022 20:26:47 -0800 In-Reply-To: <20220106042708.2869332-1-reijiw@google.com> Message-Id: <20220106042708.2869332-6-reijiw@google.com> Mime-Version: 1.0 References: <20220106042708.2869332-1-reijiw@google.com> X-Mailer: git-send-email 2.34.1.448.ga2b2bfdf31-goog Subject: [RFC PATCH v4 05/26] KVM: arm64: Make ID_AA64PFR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch adds id_reg_info for ID_AA64PFR1_EL1 to make it writable by userspace. Return an error if userspace tries to set MTE field of the register to a value that conflicts with KVM_CAP_ARM_MTE configuration for the guest. Skip fractional feature fields validation at present and they will be handled by the following patches. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 42 +++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e26027817171..f55513002281 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -801,6 +801,7 @@ #define ID_AA64PFR0_GIC3 0x1 /* id_aa64pfr1 */ +#define ID_AA64PFR1_CSV2FRAC_SHIFT 32 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 #define ID_AA64PFR1_RASFRAC_SHIFT 12 #define ID_AA64PFR1_MTE_SHIFT 8 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1eb5c5fb614f..ae9ca341a2e4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -359,6 +359,21 @@ static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, + const struct id_reg_info *id_reg, u64 val) +{ + bool kvm_mte = kvm_has_mte(vcpu->kvm); + unsigned int mte; + + mte = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR1_MTE_SHIFT); + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT. */ + if (kvm_mte ^ (mte > 0)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -390,12 +405,24 @@ static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg) id_reg->vcpu_limit_val = limit; } +static void init_id_aa64pfr1_el1_info(struct id_reg_info *id_reg) +{ + if (!system_supports_mte()) + id_reg->vcpu_limit_val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); +} + static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, const struct id_reg_info *idr) { return vcpu_has_sve(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); } +static u64 vcpu_mask_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_info *idr) +{ + return kvm_has_mte(vcpu->kvm) ? 0 : (ARM64_FEATURE_MASK(ID_AA64PFR1_MTE)); +} + static struct id_reg_info id_aa64pfr0_el1_info = { .sys_reg = SYS_ID_AA64PFR0_EL1, .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), @@ -404,6 +431,16 @@ static struct id_reg_info id_aa64pfr0_el1_info = { .vcpu_mask = vcpu_mask_id_aa64pfr0_el1, }; +static struct id_reg_info id_aa64pfr1_el1_info = { + .sys_reg = SYS_ID_AA64PFR1_EL1, + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC), + .init = init_id_aa64pfr1_el1_info, + .validate = validate_id_aa64pfr1_el1, + .vcpu_mask = vcpu_mask_id_aa64pfr1_el1, +}; + /* * An ID register that needs special handling to control the value for the * guest must have its own id_reg_info in id_reg_info_table. @@ -414,6 +451,7 @@ static struct id_reg_info id_aa64pfr0_el1_info = { #define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)]) static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = { [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info, + [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info, }; static int validate_id_reg(struct kvm_vcpu *vcpu, u32 id, u64 val) @@ -1331,10 +1369,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id) val &= ~(id_reg->vcpu_mask(vcpu, id_reg)); switch (id) { - case SYS_ID_AA64PFR1_EL1: - if (!kvm_has_mte(vcpu->kvm)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); - break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |