| Message ID | 20220209164420.8894-9-varad.gautam@suse.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add #VC exception handling for AMD SEV-ES | expand |
On Wed, Feb 9, 2022 at 8:44 AM Varad Gautam <varad.gautam@suse.com> wrote: > > Using Linux's MSR #VC processing logic. > > Signed-off-by: Varad Gautam <varad.gautam@suse.com> > --- > lib/x86/amd_sev_vc.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/lib/x86/amd_sev_vc.c b/lib/x86/amd_sev_vc.c > index 9ee67c0..401cb29 100644 > --- a/lib/x86/amd_sev_vc.c > +++ b/lib/x86/amd_sev_vc.c > @@ -147,6 +147,31 @@ static enum es_result vc_handle_cpuid(struct ghcb *ghcb, > return ES_OK; > } > > +static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) > +{ > + struct ex_regs *regs = ctxt->regs; > + enum es_result ret; > + u64 exit_info_1; > + > + /* Is it a WRMSR? */ > + exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; > + > + ghcb_set_rcx(ghcb, regs->rcx); > + if (exit_info_1) { > + ghcb_set_rax(ghcb, regs->rax); > + ghcb_set_rdx(ghcb, regs->rdx); > + } > + > + ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_MSR, exit_info_1, 0); > + > + if ((ret == ES_OK) && (!exit_info_1)) { > + regs->rax = ghcb->save.rax; > + regs->rdx = ghcb->save.rdx; > + } > + > + return ret; > +} > + > static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, > struct ghcb *ghcb, > unsigned long exit_code) > @@ -157,6 +182,9 @@ static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, > case SVM_EXIT_CPUID: > result = vc_handle_cpuid(ghcb, ctxt); > break; > + case SVM_EXIT_MSR: > + result = vc_handle_msr(ghcb, ctxt); > + break; > default: > /* > * Unexpected #VC exception > -- > 2.32.0 > Reviewed-by: Marc Orr <marcorr@google.com>
diff --git a/lib/x86/amd_sev_vc.c b/lib/x86/amd_sev_vc.c index 9ee67c0..401cb29 100644 --- a/lib/x86/amd_sev_vc.c +++ b/lib/x86/amd_sev_vc.c @@ -147,6 +147,31 @@ static enum es_result vc_handle_cpuid(struct ghcb *ghcb, return ES_OK; } +static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) +{ + struct ex_regs *regs = ctxt->regs; + enum es_result ret; + u64 exit_info_1; + + /* Is it a WRMSR? */ + exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; + + ghcb_set_rcx(ghcb, regs->rcx); + if (exit_info_1) { + ghcb_set_rax(ghcb, regs->rax); + ghcb_set_rdx(ghcb, regs->rdx); + } + + ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_MSR, exit_info_1, 0); + + if ((ret == ES_OK) && (!exit_info_1)) { + regs->rax = ghcb->save.rax; + regs->rdx = ghcb->save.rdx; + } + + return ret; +} + static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, struct ghcb *ghcb, unsigned long exit_code) @@ -157,6 +182,9 @@ static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, case SVM_EXIT_CPUID: result = vc_handle_cpuid(ghcb, ctxt); break; + case SVM_EXIT_MSR: + result = vc_handle_msr(ghcb, ctxt); + break; default: /* * Unexpected #VC exception
Using Linux's MSR #VC processing logic. Signed-off-by: Varad Gautam <varad.gautam@suse.com> --- lib/x86/amd_sev_vc.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)